CPT week May 2003Dominique Gigi CMS DAQ 1.Block diagram 2.Form Factor 3.Mezzanine card (transmitter SLINK64) 4.Test environment 5.Test done 1.Acquisition 2.Spy mode 3.Merge test 6.Next steps 7.Conclusions

CPT week May 2003Dominique Gigi CMS DAQ

CPT week May 2003Dominique Gigi CMS DAQ PCI connector 64-bit FRL Function IN_1 IN_2 IN_3 IN_4 FPGA Compact PCI 32-bit 33MHz Memory 4Mbytes Commercial Optical Link Myrinet Lanai X Compact PCI Back-plane 64kB PCI 66 or PCI-x 100MHz 66 or 100MHz Bridge FPGA

CPT week May 2003Dominique Gigi CMS DAQ CompacPCI CompactPCI bus Internal PCI bus 64bit 66MHz -Connector for NIC board -FRL FPGA -Bridge FPGA (32-bit) 2 Inputs -LVDS receivers -Buffers 64Kbytes -Connector for 2 other Inputs -FRL FPGA SRAM memory (4 Mbytes) -FRL FPGA -Memory -Bridge FPGA Place for the NIC board PCI short form factor

CPT week May 2003Dominique Gigi CMS DAQ SLink64 protocol Altera ACEX LVDS Generate 3 frequencies: -40MHz from 10 to 15 meters -60MHz from 5 to 10 meters -80MHz <= 5 meters 1 switch to choose the frequency

CPT week May 2003Dominique Gigi CMS DAQ FRL Compact PCI backplane Myrinet GIII FED emu. 32 MB for Event parameters -Event # - Bunch # - FED# - Size - Time before next Event(x100ns) Myrinet board emulated by GIII to check data and header

CPT week May 2003Dominique Gigi CMS DAQ Generic III PCI 64bit/66MHz CompacPCI GIII: -Sends event through the cable until backpressure -Sends memory address blocks -When data is coming: Checks Event data blocks and Headers FRL -Data input through Connector -Data is sent to GIII in packets + Headers Trans.

CPT week May 2003Dominique Gigi CMS DAQ FRL to ZBT memory -1 to 1024 event(s) to spy -All event to spy Bridge/FED-kit reads data from ZBT memory and sends to PC memory (Fed-kit simplify) When ZBT memory is full - a status is added at the end (when 1 to 1024) - backpressure ( acquisition mode ) (when all spy) FRL Bridge / “Fed-kit” ZBT FRL Bridge/ “Fed-kit” Myrinet ZBT PCI CPCI Events

CPT week May 2003Dominique Gigi CMS DAQ GIII FED emul. Altera ACEX 60MHz GIII FED emul. Altera ACEX 60MHz FIFO 32kB FIFO 32kB FRL ALTERA Stratrix Myricom -first test will be done with a GIII to replace the Myrinet board Events Spy Events

CPT week May 2003Dominique Gigi CMS DAQ 1.Use three GIII for merger test (2 FEDs emulator-1 Test data) 2. Go to PCI –x 100 MHz 3. Correct the schematic for next production 3bis. Extender to two additional Inputs 4. Introduce the NIOS processor inside the FRL FPGA GIII FRL

CPT week May 2003Dominique Gigi CMS DAQ 1.All parts of the PCB are tested 2.Main functions of the FRL are tested 1.Acquisition on each input 2.Spy mode through SRAM 3.PCI 64b-66MHz 4.Mezzanine transmitter board 3.Start to evaluate the cable length (3M cable) 1.5 meters (80 MHz) 2.10 meters (60 MHz) 3.15 meters (40 MHz) 4.Pending test the maximum frequency for each length 4.Pending 1.test the 100 MHz frequency for PCIx 2.test with Myrinet board 5.Full test for June (ready for production)