EE 597G/CSE 578A Project Proposal Presentation Phase-Locked Loop Han-Wei Chen & Ming-Wei Liu The Pennsylvania State University.

Slides:

Advertisements

Similar presentations

A Stabilization Technique for Phase-Locked Frequency Synthesizers Tai-Cheng Lee and Behzad Razavi IEEE Journal of Solid-State Circuits, Vol. 38, June 2003.

Advertisements

COMMUNICATION SYSTEM EEEB453 Chapter 3 (III) ANGLE MODULATION

ECE 8443 – Pattern Recognition EE 3512 – Signals: Continuous and Discrete Objectives: Generalized Fourier Transform Analog Modulation Amplitude Modulation.

Digital PM Demodulator for Brazilian Data Collecting System José Marcelo L. Duarte – UFRN – Natal, Brazil Francisco Mota das Chagas – UFRN – Natal, Brazil.

Principles of Electronic Communication Systems

Ultra Low Power PLL Implementations Sudhanshu Khanna ECE

1 Helsinki University of Technology,Communications Laboratory, Timo O. Korhonen Data Communication, Lecture5 Some Analog Systems.

EE241 Term Project - Spring 2004 Ultra low power PLL design and noise analysis EE241 Prof. Borivoje Nikolic Peter Chen, Mingcui Zhou.

Lecture 8: Clock Distribution, PLL & DLL

Lecture 7 AM and FM Signal Demodulation

S. Mandayam/ ECOMMS/ECE Dept./Rowan University Electrical Communications Systems Spring 2005 Shreekanth Mandayam ECE Department Rowan University.

 Phase detector:  Loop filter:  VCO: Phase Locked Loop (PLL) Design by Akin Akturk and Zeynep Dilli Figure 1: Basic PLL building blocks.

Oct 11, 2005CS477: Analog and Digital Communications1 FM Generation and Detection Analog and Digital Communications Autumn

Phase Lock Loop EE174 – SJSU Tan Nguyen.

Angle Modulation Objectives

Phase Locked Loop Design Matt Knoll Engineering 315.

Chapter 3 – Angle Modulation

Principles of Electronic Communication Systems

Chapter 6 FM Circuits.

FM MODULATION AND DEMODULATION. A NGLE M ODULATION To generate angle modulation, the amplitude of the modulated carrier is held constant and either the.

Phase Locked Loops Continued

Ayman Khattab Mohamed Saleh Mostafa El-Khouly Tarek El-Rifai

GUIDED BY: Prof. DEBASIS BEHERA

Lecture 22: PLLs and DLLs. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 22: PLLs and DLLs2 Outline  Clock System Architecture  Phase-Locked Loops  Delay-Locked.

Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006.

1 Phase-Locked Loop. 2 Phase-Locked Loop in RF Receiver BPF1BPF2LNA LO MixerBPF3IF Amp Demodulator Antenna RF front end PD Loop Filter 1/N Ref. VCO Phase-

BY MD YOUSUF IRFAN.  GLOBAL Positioning System (GPS) receivers for the consumer market require solutions that are compact, cheap, and low power.  This.

Motivation Yang You 1, Jinghong Chen 1, Datao Gong 2, Deping Huang 1, Tiankuan Liu 2, Jingbo Ye 2 1 Department of Electrical Engineering, Southern Methodist.

Special Topic-I PLL Basics and Design By, Anil Kumar Ram Rakhyani (akram)

Experimental results obtained from a 1.6 GHz CMOS Quadrature Output PLL with on-chip DC-DC Converter Owen Casha Department of Micro & Nanoelectronics University.

Phase-Locked Loop Design S emiconducto r S imulation L aboratory Phase-locked loops: Building blocks in receivers and other communication electronics Main.

Generation of FM Two methods of FM generation: A. Direct method:

Modulasi Sudut (2) Levy Olivia MT.

CHAPTER 15 Special ICs. Objectives Describe and Analyze: Common Mode vs. Differential Instrumentation Amps Optoisolators VCOs & PLLs Other Special ICs.

Filip Tavernier Karolina Poltorak Sandro Bonacini Paulo Moreira

1 A Low Spur Fractional-N Frequency Synthesizer Architecture 指導教授 : 林志明教授學生 : 黃世一 Circuits and Systems, ISCAS IEEE International Symposium.

McGraw-Hill © 2008 The McGraw-Hill Companies, Inc. All rights reserved. Principles of Electronic Communication Systems FM Circuits.

TELECOMMUNICATIONS Dr. Hugh Blanton ENTC 4307/ENTC 5307.

1 A Frequency Synthesizer Using Two Different Delay Feedbacks 班級：積體所碩一學生：林欣緯指導教授：林志明教授 Circuits and Systems, ISCAS IEEE International Symposium.

A 1-V 2.4-GHz Low-Power Fractional-N Frequency Synthesizer with Sigma-Delta Modulator Controller 指導教授 : 林志明教授學生 : 黃世一 Shuenn-Yuh Lee; Chung-Han Cheng;

Design And Implementation Of Frequency Synthesizer And Interrogating Phase Noise In It's Parts Advisor Professor : Dr.Sadr & Dr.Tayarani Students: Majid.

Eeng Chapter 4 Bandpass Circuits   Limiters   Mixers, Upconverters and Downconverters   Detectors, Envelope Detector, Product Detector  

Chapter 4. Angle Modulation. 4.7 Generation of FM Waves Direct Method –A sinusoidal oscillator, with one of the reactive elements in the tank circuit.

Chapter 6. Effect of Noise on Analog Communication Systems

TDTL Architecture with Fast Error Correction Technique

CS-EE 481 Spring Founder’s Day, 2003 University of Portland School of Engineering A CMOS Phase Locked Loop Authors: Dan Booth Jared Hay Pat Keller.

TELECOMMUNICATIONS Dr. Hugh Blanton ENTC 4307/ENTC 5307.

Oct 13, 2005CS477: Analog and Digital Communications1 PLL and Noise in Analog Systems Analog and Digital Communications Autumn

111 Communications Fall 2008 NCTU EE Tzu-Hsien Sang.

Phase Locked Loops VCO Ref LO PFD fLO=fref*N/M

CommunicationElectronics Principles & Applications Chapter 5 Frequency Modulation Circuits.

Clock Networks and PLLs in Altera’s Stratix III Devices VLSI Systems I Fall 2007 Hamid Abbaalizadeh.

Clock Routing CLOCK H-Tree Network Observe: Only Relative Skew is Important CLOCK Main clock driver Secondary clock drivers Reduces absolute delay. Makes.

Mackenzie Cook Mohamed Khelifi Jonathon Lee Meshegna Shumye Supervisors: John W.M. Rogers, Calvin Plett 1.

Phase-Locked Loop Design PREPARED BY:- HARSH SHRMA ( ) PARTH METHANIYA ( ) ARJUN GADHAVI ( ) PARTH PANDYA (

RF Systems Phase Detector Filter Voltage Controlled Oscillator for PLL

S Transmission Methods in Telecommunication Systems (4 cr) Carrier Wave Modulation Systems.

Eeng Chapter 4 Bandpass Circuits   Limiters   Mixers, Upconverters and Downconverters   Detectors, Envelope Detector, Product Detector  

Electronic Devices and Circuit Theory

PLL Sub System4 PLL Loop Filter parameters: Loop Type and Order

Demodulation/ Detection Chapter 4

EE 597G/CSE 578A Final Project

DESIGN AND SIMULATION OF A PHASE LOCKED LOOP FOR HIGH SPEED SERDES

PART 3:GENERATION AND DETECTION OF ANGLE MODULATION

Chapter 4 Bandpass Circuits Limiters

CMOS VLSI Design Chapter 13 Clocks, DLLs, PLLs

Phase-Locked Loop Design

VLSI Project Presentation

CMOS VLSI Design Chapter 13 Clocks, DLLs, PLLs

Lecture 22: PLLs and DLLs.

Presentation transcript:

EE 597G/CSE 578A Project Proposal Presentation Phase-Locked Loop Han-Wei Chen & Ming-Wei Liu The Pennsylvania State University

Outline Introduction Architecture & Elements Application Specification Timeline

Introduction Phase Lock Loop: PLL is a closed-loop feedback control system that maintains the phase of a signal is a fixed relationship to a reference signal.

Introduction Major source of power dissipation are the VCO and frequency divider. A frequency-locked loop synthesizer may not require a frequency divider. 1/R PDF VCO 1/N Loop Filter 10MHz 1/10 900MHz 1/900 Integrator

Outline Introduction Architecture & Elements Phase and Frequency Detector and charge Pump Loop Filter VCO

PFD with charge pump Compare the phase and Frequency of reference signal and oscillator. Output a current that has an average DC value proportional to the phase error. R2 C2 C1 PFD & Current Charge Pump R V

Phase and Frequency Detector

Loop Filter 1st-order Steady-State phase error [Zie] 2nd-order or higher Avoid SS phase error Reduce the spur levels [Des b]

Voltage-Control Oscillator Using Ring OSC to implement: Odd number of inverters Frequency is controlled by changing the bias of the buffers and hence control the delay. [stanford]

Reference [Zie] Principles of Communication: Systems, Modulation and Noise, Wiley; 5 edition (July 27, 2001), R.E. Ziemer [Des b] PLL Performance, Simulation, and Design [stanford] /

Outline Introduction Architecture & Elements Application Specification Timeline

Application Since PLL is used for synchronization, its application domain largely resides in various communication domain They are used for: Clock generation Clock recovery Deskewing Spread Spectrum

Application Ex: A network router that transmit data over a certain range, a PLL is good at maintaining a constant phase angle relative to a reference signal (i.e. clock synchronization between the host and the client).

Application This is especially useful when the data and clock are sent together over a common cable (such as in Manchester coding)

Application Other applications like: Deskewing (on the receiver side) If the clock is sent parallel with data Clock generation Precise clock phase even at high frequency Ability of fast switching among different frequencies (Settling Time) can impact system’s response time Demodulation FM Radio, Modem

Outline Introduction Architecture & Elements Application Specification Timeline

Specification As a reference, we took a snapshot of the LM565, a PLL-IC by National Semiconductors

Specification Specification (subject to change)

Outline Introduction Architecture & Elements Application Specification Timeline

WeekScheduleActualRemarks (1) 2/5-2/11 Initial, Bkgnd Study In ProgressProposal Due (2) 2/12-2/18 PFD (Phase Freq. Detector) (3) 2/19-2/25 PFD / Charge Pump (4) 2/26-3/4 Charge PumpLots of Midterms (5) 3/5-3/11 Loop FilterSpring Break (6) 3/12-3/18 Loop Filter / Freq. Divider Progress Due (7) 3/19-3/25 VCO (V Contd. Oscillators) (8) 3/26-4/1 VCO (9) 4/2-4/8 Bug Fix / Report (10) 4/9-4/15 FinalizeFinal Due Timetable

Thank You! Any question or comment? ;-)