CISC 3595 Operating Systems Introduction Tuesday / Friday 10:00-11:15am X. Zhang

Four Components of a Computer System 2 People, machines, other computers CPU, memory, I/O devices

What is an Operating System? 3 A program that acts as an intermediary between a user of a computer and the computer hardware Operating system goals: – Execute user programs and make solving user problems easier – Make the computer system convenient to use – Use the computer hardware in an efficient manner

Computer System Organization 4  One or more CPUs, device controllers connected through common bus providing access to shared memory

A quick tour of computer hardware  Basic Elements  Processor  Instruction Execution  Interrupts  The Memory Hierarchy  Cache Memory  I/O Communication Techniques 5

Basic Hardware Elements  Processor or Central Processing Unit (CPU)  Controls operation, performs data processing  Memory (main/primary memory)  Volatile, i.e., data is typically lost when power is removed  Used to store data and instructions  I/O Modules: disk controller, USB controller,...  Moves data between computer and external device such as storage (e.g. hard drive), communication equipment, terminals  System Bus  Wires or backplane connecting CPUs, I/O modules and main memory 6

Top-Level Logic View 7 Main memory: a large array of words or bytes. Each words has its own address.

Roadmap  Basic Elements  Processor  Instruction Execution  Interrupts  The Memory Hierarchy  Cache Memory  I/O Communication Techniques 8

Processor (CPU)  CPU: the physical heart of entire computer system  ALU: Arithmetic Logic Unit  Registers 9

Singleprocessor & Multiprocessor 10  Most systems use a single general- purpose processor  Multiprocessors systems growing in use and importance  parallel systems, tightly-coupled systems  Advantages include 1. Increased throughput 2. Economy of scale 3. Increased reliability – graceful degradation or fault tolerance

Processor Registers  Storage in CPU; Faster and smaller than main memory  Data/Address registers  Storing data or memory address  Store frequently used variable in register: for (register int i = 0; i < bufsize; i++) * p++ = assigned_val;  Control and status registers  Used to control CPU operation  Ex: Program counter (PC), Instruction register (IR),  Ex: Program status word (PSW): contain bits set by processor hardware as a result of operations  e.g., to denote an exception (arithmetic operation overflow…) 11

Roadmap  Basic Elements  Processor Registers  Instruction Execution  Interrupts  The Memory Hierarchy  Cache Memory  I/O Communication Techniques 12

Instruction Execution  A program: a sequence of instructions stored in memory (main memory or disk)  To run a program, it needs to be loaded (from disk) into main memory  Basic Instruction Execution cycle:  Processor reads (fetches) instruction from main memory  Processor executes the instruction Stored program computer (due to John von Neumann ( )) 13

Instruction Fetch and Execute  Program counter (PC)  holds address of the instruction to be fetched next  Processor fetches the instruction from memory, & increments PC  Fetched instruction is loaded into instruction register (IR)  Decoded, and executed by ALU if it’s an arithmetic and logic operation 14

Machine Code  Instruction set: the set of machine instructions that a processor can execute  Main categories of machine instructions  Processor-memory: move data between memory and processor  processor-I/O: move data between peripheral device and CPU  Data processing: arithmetic or logic operation on data  Control: alter execution sequence (jump, if and loop structure) 15

Machine code and Assembly Language  Process only understands binarys => machine instructions are coded in binary strings  e.g., (Hexadecimal: B0 61)  Assembly language: mnemonic language (helping to remember)  MOV AL, #61h  Move the value 61h (or 97 decimal; the h-suffix means hexadecimal; the pound sign means move the immediate value, not location) into the processor register named "AL".  If a certain process supports 50 different instructions, how many bits are needed to represent the type of the instruction ? 16

Considering a Hypothetical Machine 17

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So far so good  We learnt how a program is executed by CPU: follow the instructions (program)  Now think about the following simple program:  To read two integers from standard input, add them and print the result on the display  How to do I/O?  Wait ? Too wasteful of processor resource  Also not fair if multiple users are working on the computer (such as our storm server)  Need some way to interrupt current program execution to give CPU to other user program or to handle I/O response 19

Roadmap  Basic Elements  Processor Registers  Instruction Execution  Interrupts  The Memory Hierarchy  Cache Memory  I/O Communication Techniques 20

Interrupts  A mechanism to interrupt normal sequencing  One goal: to support interrupt-I/O that improve process utilization  Most I/O devices are slower than CPU => inefficient for processor to wait for I/O to complete  With Interrupt mechanism:  CPU can execute other process/job after issuing I/O command  I/O module generates an interrupt to notify CPU about completion of the I/O operation or failure. 21

Transfer of Control via Interrupts 22 Interrupt Handler: Predefined routines to be called when a certain interrupt occurs.

Simple Interrupt Processing 23

Different Types of Interrupts  Program: arithmetic overflow, division by zero, illegal machine instruction, reference outside of user’s allowed memory space, also called exception, trap or software interrupt  Timer: generated by a timer with CPU  I/O: generated by I/O controller to signal completion of operation or error condition  Hardware failure: triggered by power failure, memory parity error… 24 An operating system is interrupt driven.

Multiprogramming 25  Single program cannot keep CPU and I/O devices busy  Multiprogramming organizes programs so CPU always has one to execute  Multiple programs(jobs) is kept in memory  One program is selected and run via job scheduling  When it has to wait (for I/O for example), OS switches to another job  After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt

Roadmap  Basic Elements  Processor Registers  Instruction Execution  Interrupts  The Memory Hierarchy  Cache Memory  I/O Communication Techniques 26

Main (Primary) Memory 27  Main memory – the only large storage media that CPU can access directly  Capacity:  Bandwidth  Peak: one word per bus cycle  Local bus, i.e., system bus

Secondary Storage 28  Hard disk: extension of main memory that provides large nonvolatile storage capacity  disk controller: determines logical interaction between the device and the computer  Performance measure  Maximum transfer rate: 66Mb/s  Spindle Rotation Speed: decides the reading/writing rate  Seek time: avg time to locate the data

Why so many different memory/storage  Major constraints in memory  Amount  Speed  Expense  Generally:  Faster access time, greater cost per bit  Greater capacity, smaller cost per bit  Greater capacity, slower access speed 29

Memory Hierarchy  Major constraints in memory  Amount  Speed  Expense  Going down hierarchy  Decreasing cost per bit  Increasing capacity  Increasing access time  Decreasing frequency of access Auxiliary memory External and nonvolatile Used to store program and data files 30

Performance of Various Levels of Storage 31 ns: nanosecond (10 -9 seconds), 1 billionth second < 16 GB

Caching is everywhere 32  Caching: information in use is copied from slower and larger storage to faster and smaller storage (cache) temporarily  Faster storage (cache) checked first to determine if information is there  If it is, information used directly from the cache (fast)  If not, data copied to cache and used there  Caching is performed at many levels in a computer  Hardware: L1 cache  Operating system: disk cache  Software/application level caching

Primary Cache (L1 cache)  Processor must access memory at least once per instruction cycle  Processor speed faster than memory access speed  Storage on CPU for temporary storage of instructions and data.  fastest form of storage. (on-the-chip with a zero wait-state (delay) interface to the processor's execution unit,)  Exploit locality with a small fast memory  Data which is required soon is often close in memory to the current data  Temporal locality and spatial locality 33

Primary Cache and Main Memory Cache contains copy of a portion of main memory Processor first checks cache If not found, block of memory read into cache Because of locality of reference, likely future memory references are in that block 34

Roadmap  Basic Elements  Processor Registers  Instruction Execution  Interrupts  The Memory Hierarchy  Cache Memory  I/O Communication Techniques 35

Input/Output Device Controller 36 Each is in charge of a particular type of device Execute concurrently with CPU Responsible for I/O operation: moving data between the device and the controller’s local buffer

I/O Techniques  When CPU encounters an instruction relating to I/O,  it executes that instruction by issuing a command to the appropriate I/O module  Three techniques are possible for I/O operations:  Programmed I/O  Interrupt-driven I/O  Direct memory access (DMA) 37

Programmed I/O  The I/O module performs the requested action  then sets the appropriate bits in the I/O status register  but takes no further action to alert the processor.  As there are no interrupts, CPU must determine when I/O is complete  Wait instruction idles CPU until the next interrupt  At most one I/O request is outstanding at a time, no simultaneous I/O processing 38

Programmed I/O Example  Data read in a word at a time  Processor remains in status-checking loop while reading 39

Interrupt-driven I/O 40  When CPU encounters an I/O related instruction  it executes that instruction by issuing a command to appropriate I/O module  After I/O starts, control returns to user program without waiting for I/O completion  After I/O device controller finish I/O operation, it generate an interrupt to inform CPU  CPU, in the interrupt handler, read the data from device controller or write next block of data to device controller  Wake up processes waiting for the interrupt...

Direct Memory Access (DMA) I/O 41  DMA: allow device to access memory for reading and/or writing independently of CPU.  Used in high-speed I/O devices: disk controllers, graphics cards, network cards and sound cards  DMA module (DMA device controller)  Transfers blocks of data from buffer storage directly to main memory  Only one interrupt is generated per block  CPU only involved at beginning and ending transfer.  Less CPU intervention => much more efficient in terms of processing times

DMA I/O: How does it work?  When needing to read/write processor issues a command to DMA module with:  Whether a read or write is requested  Address of the I/O device involved  Starting location in memory to read/write  Number of words to be read/written 42

How a Modern Computer Works 43