Trieste, 8-10 November 1999 CMOS technology1 Design rules The limitations of the patterning process give rise to a set of mask design guidelines called.

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Presentation transcript:

Trieste, 8-10 November 1999 CMOS technology1 Design rules The limitations of the patterning process give rise to a set of mask design guidelines called design rules Design rules are a set of guidelines that specify the minimum dimensions and spacings allowed in a layout drawing Violating a design rule might result in a non-functional circuit or in a highly reduced yield The design rules can be expressed as: –A list of minimum feature sizes and spacings for all the masks required in a given process –Based on single parameter that characterize the linear feature (e.g. the minimum grid dimension). base rules allow simple scaling

Trieste, 8-10 November 1999 CMOS technology2 Design rules Minimum line-width: –smallest dimension permitted for any object in the layout drawing (minimum feature size) Minimum spacing: –smallest distance permitted between the edges of two objects This rules originate from the resolution of the optical printing system, the etching process, or the surface roughness

Trieste, 8-10 November 1999 CMOS technology3 Design rules Contacts and vias: –minimum size limited by the lithography process –large contacts can result in cracks and voids –Dimensions of contact cuts are restricted to values that can be reliably manufactured –A minimum distance between the edge of the oxide cut and the edge of the patterned region must be specified to allow for misalignment tolerances (registration errors)

Trieste, 8-10 November 1999 CMOS technology4 Design rules MOSFET rules –n+ and p+ regions are formed in two steps: the active area openings allow the implants to penetrate into the silicon substrate the nselect or pselect provide photoresist openings over the active areas to be implanted –Since the formation of the diffusions depend on the overlap of two masks, the nselect and pselect regions must be larger than the corresponding active areas to allow for misalignments

Trieste, 8-10 November 1999 CMOS technology5 Design rules Gate overhang: –The gate must overlap the active area by a minimum amount –This is done to ensure that a misaligned gate will still yield a structure with separated drain and source regions A modern process has may hundreds of rules to be verified –Programs called Design Rule Checkers assist the designer in that task