Brian Bailey Interfaces Technical Committee.

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Presentation transcript:

Brian Bailey Interfaces Technical Committee

ITC – BB Agenda Welcome and Introduction – Vassilios Gerousis Rules of operation - Vassilios Structural Organization - Brian Charter and Objectives - Brian First Steps - Brian

ITC – BB Where we Fit IEEE HDL+ TCC (Vassilios Gerousis) Formal property language (VFV) Ch: Harry Foster Verilog-AMS Ch: VG (temp) Co: Sri (temp) Verilog++ Ch: VG. C0: D. Kelf SLDL (Rosetta) Perry and David ALF SLDL Semantics Roberto SDFVerilog Synthesis VHPI-AMS Planned Changes Existing Committees Assertion Ch: John Emmit C0: Dan Fitz Interfaces Ch: BB Co Ch: ?? Interfaces Ch: BB Co Ch: ?? New Committees VHPI

ITC – BB Interface TC Functional Space Abstract Interpretation Cycle-True Simulation Functional Simulation SW based HDL sim. HW based RSP Production Silicon Thanks to: Maurizio Vitale Philips Semiconductors

ITC – BB Interface TC Tool Space Its difficult to build complete verification environments when they don’t talk –Does not imply 1 interface to do everything HDL Simulators Co-Simulators Abstract Software Debuggers Testbench Components Emulators Prototypes C Based UML ? Verification Plan Checkers Accelerators ISS

ITC – BB Organizational Issues This Technical Committee will continue to work on the definition of the big picture. Additional sub-committee to work on aspects identified by TC –Transaction to emulator (needs to be broadened to transaction to pin) –Transaction to transaction –ISS –Others ?

ITC – BB Main TC Charter To identify and standardize multi-abstraction and multi-domain interfaces to enable complete virtual prototypes to be constructed. Goals: –Produce roadmap for TC by DAC –Complete 1 Accellera standard within 2002 –Have draft of at least one other

ITC – BB First Steps Need a co-chair for this group. Need technical chairs for the sub-groups. Would like to identify the objectives of the group members. Would like to identify additional members.