D0 PMG, 07Jun05 1 D. Wood, Trigger Upgrade Status Trigger Upgrade Status  The DØ Trigger Upgrade consists of u Complete replacement of Level 1 calorimeter trigger u Replacement of the DFEA’s (track finding modules) in the Level 1 Central Track Trigger u A new Level 1 system to match calorimeter objects and tracks (L1caltrack) u Upgraded/additional processors for the Level 2 trigger (L2beta) u Incorporation of Layer 0 into the Level 2 Silicon Track Trigger (L2STT)

D0 PMG, 07Jun05 2 D. Wood, Trigger Upgrade Status The Run IIb Trigger System CAL c/f PS CFT SMT MU FPD L1Cal L1PS L1CTT L1Mu L1FPD L2Cal L2PS L2CTT L2STT L2Mu Global L2 Framework Detector Lumi Level 1 Level MHz2.5 kHz1 kHz L3/DAQ Level 3 50 Hz Cal-TRK MU-TRK New (or replaced) System Enhanced System

D0 PMG, 07Jun05 3 D. Wood, Trigger Upgrade Status Management structure WBS 1.2: Trigger Upgrade P. Padley (Rice), D. Wood (Northeastern) WBS 1.2.1: Level 1 Calorimeter M.Abolins(MSU), H.Evans(Columbia) WBS 1.2.2: Level 1 Cal-track match K. Johns (Arizona) WBS 1.2.3: Level 1 Tracking M. Narain (Boston), Don Lincoln (FNAL) WBS 1.2.4: Level 2 Beta upgrade R. Hirosky (Virginia) WBS 1.2.5: Level 2 STT upgrade U. Heintz (Boston) WBS 1.2.6: Trigger Simulation M. Hildreth (ND), E. Barberis (NEU)

D0 PMG, 07Jun05 4 D. Wood, Trigger Upgrade Status L1cal Milestone: “L1 Calorimeter Trigger Production and Testing Complete” – Achieved 04/29/05  This means u All active boards produced and bench tested u Crates, power supplies in hand u Enough good boards in hand for full system (including spares)  Remaining work u BLS-ADF transition system u Continued integration testing and pre- commissioning at Fermilab

D0 PMG, 07Jun05 5 D. Wood, Trigger Upgrade Status L1 Cal system BLS 2 EM + 2 H   EM H ADC + Digital- Filter (ADF) x 80 ADC + Digital- Filter (ADF) x 80 Trig Algo ’ s (TAB) x 8 Trig Algo ’ s (TAB) x 8 Global + Control (GAB) x 1 Global + Control (GAB) x 1 ADF Timing Fanout 1280 Existing BLS Cards 2560 EM +HAD TT 0.2x0.2 TT Signal Processing 8-bit TT Et Sliding Windows clusters sums Global Sums Framework Interfaces Timing (SCL) L2 & L3 Control (TCC) FrameworkFramework Jets EM Tau Et,Mpt timing/ctrl/vme timing/ctrl Cal-Trk Match encoded clusters Signals from L1 Track VME Interface & SCL Interface 16 EM 16 H BLS-to-ADF Transition System Patch Panel Cards (x80) Pleated Foil Cables (x160) Paddle Cards (x80) BLS-to-ADF Transition System Patch Panel Cards (x80) Pleated Foil Cables (x160) Paddle Cards (x80) 1280 Existing BLS Trigger Cables

D0 PMG, 07Jun05 6 D. Wood, Trigger Upgrade Status L1cal ADC Digital Filter (ADF)  Largest production of the trigger upgrade (80 cards needed)  ADFv2 done by MSU u production readiness review 02/11/05 – no modifications needed u production complete 4/4/05 u all cards bench tested at MSU 4/29/05 u ~2 month gain on schedule estimated in Feb u 100 good cards s only 3 required minor reworking u full crate tests completed at MSU in May

D0 PMG, 07Jun05 7 D. Wood, Trigger Upgrade Status L1cal TAB and GAB  TAB production and bench testing finished in January (already reported at last Director’s Review) u 12 available = spares  GAB production and bench testing finished in February u 3 available = spares  several production modules at Fermilab for integration tests  EM sliding window algorithm (firmware) updated based on performance on real Run IIa electron data

D. Wood, Trigger Upgrade Status MCH Configuration Color coding illustrates the old & new TT readout. Old New J. Fogelsong (2004)

D0 PMG, 07Jun05 9 D. Wood, Trigger Upgrade Status BLS-ADF transition system  engineering review held Mar 25 – current design emerged  80 patch panels & transition cards, 160 cables  Added to the project recently with change control u New milestone: “Transition system complete”, foreseen 7/15/05  Necessary for installation  reqs went out in May for u 25 (of 40) patch panel cards u all patch panel chassis u 182 pleated foil cables (10 already in hand and tested) u 25 transition card  expect prototype system in hand by Jun 17 – allows larger scale testing of L1cal system

D. Wood, Trigger Upgrade Status Run IIb L1 Calorimeter Trigger Control Path L1Cal Expert Programs L1Cal TCC COOR Monitoring Clients Bit3 V.I. Master (to ADF) V.I. Master (to VRB) VME/SCL (to TAB) SCL Distributor (to ADF) L1Cal Comm. Crate VME-9U ADF Crate #1 of 4 VME-6U ADF #20 V.I. Slave ADF #20 … ADF Crate #4 of 4 VME-6U ADF #20 V.I. Slave ADF #1 … … TAB/GAB Crate Custom-9U TAB #1TAB #8GAB … L1Cal Readout Crate VME-9U V.I. Slave VRB VRBCSBC L3 L2 Ethernet Optical Fiber Splitters to L2Cal Crate … P. Laurens Rev: 31-May-05 (ALS, PAL) TFW SCL

D0 PMG, 07Jun05 11 D. Wood, Trigger Upgrade Status L1Cal integration: finished tasks  all input/output signal transmissions verified at “hello world” level except GAB-to- L2/L3 and GAB-to-TFW  real calorimeter signals sent via splitter to ADF and oversampled data recorded for offline study  test data written from TAB to tape via DZero DAQ chain u part of real DZero run u data unpacked offline with prototype unpacker  long term test of ADF-to-TAB data transmission with pseudorandom data: u bit error rate <

D0 PMG, 07Jun05 12 D. Wood, Trigger Upgrade Status L1Cal integration: still to do  run data through full chain: BLS-splitter-ADF- TAB-VRB-SBC-Level3-tape u expected next few days  test two fully loaded TAB inputs from 20 ADF’s u requires BLS transition system prototype cards  AND/OR terms transmitted to Trigger Framework  stable data to L2/L3 u bit error rate presently too high  GAB-to-L2/L3, GAB-to-TFW  send data to L1caltrack match system  set up analog pulser run and analysis  System review for L1cal (organized like a PRR) being scheduled for mid/late July

D0 PMG, 07Jun05 13 D. Wood, Trigger Upgrade Status L1caltrack match trigger  Production is finished  Testing u Crate managers (MTCM) – 2 of 6 tested u MTCxx (motherboard) – 2 of 12 tested u Flavor board (daughterboard) 12 of 14 tested  Commissioning u In January, certified message sending to Level 1 and Level 3 with old MTCM. u New MTCM, check that sychronization was stable over extended period (tested ~30 min) u To do in near future s Read out both trigger crate and MTM crate s Re-verify message sending to L3 with new MTCM s Check trigger and readout with new MTCxx

D0 PMG, 07Jun05 14 D. Wood, Trigger Upgrade Status L1caltrack, continued  Cabling u Most collision hall cables run and terminated last year u Still to be done (getting FNAL help through Curtis Danner) s Terminate the L1CTT backplane cables (180) s backplane-L1caltrack pigtail (180) s Terminate some remaining on-board MTCxx cables (65)  Software u “one button” coldstart and restore GUI exists u Trigger crate and MTM crate messages checked in trigger simulator s Unpacking code complete s Beginning work on unpacking to TMB++ and CAF data formats (where typical users access the data)

D0 PMG, 07Jun05 15 D. Wood, Trigger Upgrade Status L1CTT  Hardware is essentially done u Crates, controllers and backplanes (Fermilab) done last year – some firmware work continues u DFEA2 production and testing completed at BU in May (ahead of schedule) s 40 DFEA2’s needed for full system – 60 were produced –50 good boards at Fermilab –7 good boards at BU –3 bad boards  Pre-commissiong u Parallel chain used to show that existing L1CTT and new DFEA2’s give identical results on real data when same equations were loaded (Feb)

D. Wood, Trigger Upgrade Status Closeup of DFEII crate DFE2A DFE2 Controller DFE2 Controller

D0 PMG, 07Jun05 17 D. Wood, Trigger Upgrade Status L1CTT parallel chain MixerDFEA crates (current) CTOC, etc Fiber signals from AFE LVDS splitters Partial prototype DFEA crate (upgrade) Prototype crate controller (upgrade) PC link Trigger framework timing (Serial command link) Parallel slice of upgrade prototypes was installed during 2004 shutdown and is being used to pre-commission upgrade components Extra CTOC, CTTT Data stream

D0 PMG, 07Jun05 18 D. Wood, Trigger Upgrade Status CTT: DFEA – DFEA2 comparison (on data) first 4 bins show sectors with both RunIIa and RunIIb electronics histo: IIa points: IIb agreement is exact

D0 PMG, 07Jun05 19 D. Wood, Trigger Upgrade Status L1CTT  What remains u Testing full crates & other system tests at Fermilab u Track finding equations for all sectors u Evaluate efficiency of new equations from parallel chain data u System review: late July u Projected date for completing all tests and preparations ~mid August (May updates not in MPP yet)

D0 PMG, 07Jun05 20 D. Wood, Trigger Upgrade Status L2beta upgrade  “Drop-in” replacement of Single Board Computers (SBC’s) in Level 2 system  Selected SBC: Adlink 6820 u Dual 2.4 GHz PIV u 64 bit/66 MHz PIC Bus  Testing u Few weeks of running at UVa u ~2 weeks at DØ running online executable in shadow mode u Smooth sailing – no problems

D0 PMG, 07Jun05 21 D. Wood, Trigger Upgrade Status L2beta Production Readiness Review  Reviewed April 15 th  Committee: Reinhard Schwienhorst (chair), Gustaaf Brooijmans, Drew Baden  Review charge u Technical compatibility of board u Review of testing u Power & cooling u CPU needs and numbers  Recommendation: procure 9 of these SBC’s

D0 PMG, 07Jun05 22 D. Wood, Trigger Upgrade Status Level 2 CPU vs. Lum

D0 PMG, 07Jun05 23 D. Wood, Trigger Upgrade Status Level 2 STT  Buffer controller production u Complete in May – received at Nevis u One misrouted trace fixed by wire soldered onto board  Silicon Track Cards (STC’s) tested at BU  Track Fit Card (TFC) code modification (for Layer 0) ongoing at Stony Brook

D0 PMG, 07Jun05 24 D. Wood, Trigger Upgrade Status Trigger latency adjustment  To accommodate latency of the upgraded L1 trigger, the overall L1 trigger latency must be increased from 3300 ns to 4092 ns (6 BC ticks) u critical timing path is L1cal-to-L1caltrack-to-TFW u Pipelines in calorimeter, silicon, CFT can accommodate this increase u PDT and scintillator front-ends must be modified s Mostly firmware mods but the PDT Contrl Boards must be removed from the collision hall u requires collision hall access to swap PDT boards u timing shift needs to be coordinated with all front end systems

D0 PMG, 07Jun05 25 D. Wood, Trigger Upgrade Status Coupling with shutdown  Coupling with installation schedule/timing u L1cal: high – no collision hall access needed, but several weeks of downtime necessary u L1CTT: moderate – access needed, but shorter installation u Other systems: low – can be installed almost any time with little/no interruption of experiment

D0 PMG, 07Jun05 26 D. Wood, Trigger Upgrade Status Summary  Hardware production is essentially complete u Exception: passive transition system for L1cal BLS signals  Largest productions went extremely well u ADFv2 at MSU, 100 tested boards, ~2.5 months ahead of schedule u DFEA2 at BU, 57 tested boards, ~2 months ahead of schedule  The trigger upgrade was largely university-based, but almost all action has now moved to Fermilab for system integration and pre-commissioning  Significant system reviews scheduled for July (L1cal and L1CTT) – last internal reviews in the project  Main thrust now is to do as much commissioning as possible before installation