SL-PGA firmware overview M. Sozzi Pisa - January 30/31, 2014

Overview Distribute clocks and timing signals to PPs Collect trigger primitives from PPs and merge them Possibly merge primitives with those from another TEL62 Pass primitives to another TEL62 or produce final sub-detector primitives Assemble packets with multiple primitives Distribute L0 triggers to PPs Collect triggered data from PPs and merge them Assemble multi-event packets Send primitives and main data through ethernet Handle CHOKE/ERROR lines

SPI3T X SPI3R X Header mem TX mem Data packet sender TX hdr mem Header builder MEP assembler QDR mux MEP info FIFO MEP data FIFO MEP location mem Data header FIFO MEP length FIFO Evt data FIFO Evt length FIFO Event generator Event generator mem RX mem Event merger PP data FIFO ECS MON ECS MON Test FIFO 1 ECS QDR EC S SL-FPGA DATA = OK = In test TTC handler Timestamp FIFO Type FIFO Trigger dispatcher P TTCrx Gbit Data builder ECS Data distributor Hdr mem arbiter Event mux Check summer PP-SL tester Test mem 1 ECS P P Intlb tester QPLL monitor Choke Error EC S MON Logger Log FIFO EC S SL data FIFO SL data source ECSMON Triginfo FIFO Trigger generator EC S Choke generator EC S = accessible from CCPC MON = monitored FIFO QDR interface

Header builder MTP assembler MTP data FIFO Trig header FIFO MTP length FIFO Primitive length FIFO Fake primitive generator Primitive merger PP trig FIFO EC S MON EC S MON SL-FPGA TRIG = OK = In test Trig builder EC S Trig distributor Primitive mux Check summer PP-SL tester Test mem 1 ECS P P MON SL trig FIFO SL trig source ECSMON Trig packet sender MTP buffer EC S Primiitive data FIFO EC S MON Primitive generator mem EC S MTP info FIFO EC S MON Timestamp updater TX hdr mem SPI3T X Choke generator EC S = accessible from CCPC MON = monitored FIFO Inter TEL controller Prev- next boards

A few random remarks Ethernet interface is fully home-made (no IP cores used anywhere) Jumbo frames and IP fragmentation implemented

SL-FPGA Firmware version: 0x0002 Build: 0x7d1 (2001) [27/01/ :31] Sub-detector: 0x00 [GENERIC] Source ID: 0x0 Sub-ID: 0x0 FW version: 0x01(1) Clock phases: PP0: 0x15 PP1: 0x15 PP2: 0x15 PP3: 0x15 GbE EPROM: Unprotected PP-FPGA enable: [-123] Trigger: ON TTC: ON SOB/EOB: ON Offset: 0xfc0 ( us) Type timeout: 128 (3200 ns) Local trigger: OFF ECS trigger: Type: 0x00 Multi: OFF Logger: ON (L) Mask: 0x0008 Freeze manager: OFF Choke manager: 0x0f Error manager: 0x Pri generator: OFF Repeat: infinite TS adjust: OFF Pri merger: OFF MTP assembler: OFF Primitives/MTP: 1 Max latency: 40.0 us TS checks: YES Trig builder: OFF Trig sender: OFF Evt generator: OFF Repeat: infinite Evt merger: ON MEP assembler: ON Events/MEP: 1 MEP/port: 1 Data builder: ON Data sender: ON Max data payload: 1472 bytes MEP/address: 1 Dynamic addresses: Trig: 0 Data: 0 TX trigger flow: OFF Ports: ---- TX data flow: ON Ports: 0--- TX GbE RX flow: OFF Ports: ---- TX memory flow: OFF Ports: ---- Words: 0 GbE TX marker: packet 0 out of 0 (128 ns duration) RX ARP flow: OFF Ports: ---- RX mirror flow: OFF Ports: ---- RX memory flow: OFF Ports: ---- slinfo

SL-FPGA Mode: RUN Status: 0x001401fd Error: 0x [ TRDIS BURST ] Running since: 4244 s (435 bursts) Burst: END TS at last EOB: 0xf7fffff (6.50 s) QPLL lock: OK Lock lost: 0 ( 0.00 us) TTC: Ready TTC: Broadcast FIFO: 256 IAC FIFO: 0 Single err: 0 Double err: 0 TTC Triggers: Timestamp: 0 [E ] Max: 1 [ ] (459.8 kHz) TTC Messages: Trig type: 0 [E ] Max: 1 [ ] Trig dispatch: Triginfo: 0 [E ] Max: 8 [ ] Phys: Choke: 0 [PP: 0000 SL: 0 ] Monitor: 0 [PP: 0000 SL: 0] Count: 0 Time: 0 us Error: - [PP: 0000 SL: 0 ] Monitor: - [PP: 0000 SL: 0] TRIG FLOW Trig IB0 (PP0): 0 [E ] Max: 0 [ ] Total: 0 Trig IB1 (PP1): 0 [E ] Max: 0 [ ] Total: 0 Trig IB2 (PP2): 0 [E ] Max: 0 [ ] Total: 0 Trig IB3 (PP3): 0 [E ] Max: 0 [ ] Total: 0 Trig IB4 (SL): 0 [E ] Max: 0 [ ] Total: 0 Trig merger: Data: 0 [E ] Length: 0 [E ] Max: 0 [ ] 0 [ ] MTP assembler: Info: 0 [E ] Buffer: 0 [E ] Max: 0 [ ] 0 [ ] Primitive count: 0 MTP count: 0 MTP words count: 0 Trig builder: Header: 0 [E ] Data: 0 [E ] Length: 0 [E ] Max: 0 [ ] 0 [ ] 0 [ ] DATA FLOW Data IB0 (PP0): 0 [E ] Max: 0 [ ] Total: 0 Data IB1 (PP1): 0 [E ] Max: 301 [ ] Total: Data IB2 (PP2): 0 [E ] Max: 324 [ ] Total: Data IB3 (PP3): 0 [E ] Max: 35 [ ] Total: Data IB4 (SL): 0 [E ] Max: 31 [ ] Total: Data merger: Data: 996 [ ] Length: 0 [E ] Max: 996 [ ] 1 [ ] MEP assembler: Info: 0 [E ] Buffer: 0 [E ] Max: 3 [ ] 237 [ ] Event count: MEP count: MEP words count: Data builder: Header: 0 [E ] Data: 0 [E ] Length: 0 [E ] Max: 6 [ ] 14 [ ] 1 [ ] OUTPUT TX flows: Trig: 0 Data: SPI3RX: 0 TXMEM: 0 TX ports: 0: : 0 2: 0 3: 0 (MB/s): 0: : : : (Max): 0: : : : GbE TX pause: Trig: 0 Data: 0 Time: 0 ms (0.00) Last pkt words: 53 (<= 212 bytes) slstatus

GBE PORT #0 PORT #1 PORT #2 PORT #3 Link status: 1G FD UP 1G FD UP 1G FD UP 1G FD UP TX bytes OK (last): TX bytes BAD (last): TX packets (last): RX bytes OK (last): RX bytes BAD (last): RX packets (last): Autoreset watchdog: NO Frame sync: OK DLL: OK PLL: OK Bunch counter: 540 Event counter: Single errors: 0 Double errors: 0 SEU errors: 0 gbestatus ttcrxstatus

Data format

Missing/coming Trigger primitive transmission at periodic interval Self-triggering mode using (lowest 8bit of) generated primitives Inter-TEL communication (and primitive merging) Ping implementation More error protection (e.g. QDR overflow) More error handling/recovery Proper handling of all special triggers Full propagation of backpressure (to CHOKE) Removal of asynchronous resets, completion of error persistence High-statistics internal tests