A 3-V Fully Differential Distributed Limiting Driver for 40 Gb/s Optical Transmission Systems D.S. McPherson, F. Pera, M. Tazlauanu, S.P. Voinigescu Quake Technologies, Inc. Ottawa, ON, K2K 2T8, Canada

Tuesday, October 22, 2002Slide 2E.1 Outline Overview Device modeling Circuit design and features Measurement results Summary

Tuesday, October 22, 2002Slide 3E.1 Design overview Fully differential AC coupled at the input DC coupled to the modulator Based on a 0.15  m GaAs PHEMT technology Uses double source follower inverter gain stages Output drive stage is distributed Operates in limiting mode Includes additional control features

Tuesday, October 22, 2002Slide 4E.1 Scalable PHEMT model extraction An accurate scalable model is essential for this design It must capture the transistor’s characteristics over the entire bias range For the present design, the Agilent EEsof Scalable Nonlinear HEMT model was used The model is implemented in Agilent EEsof EDA’s Advanced Design System

Tuesday, October 22, 2002Slide 5E.1 Extraction geometries and conditions Gate geometries 1 x 10  m 2, 1 x 20  m 2, 1 x 40  m 2 2 x 40  m 2, 2 x 60  m 2 V gs −0.9 V … +0.5 V V ds 0 V … 5.0 V Frequency45 MHz … 50 GHz Temperature18 °C and 100 °C

Tuesday, October 22, 2002Slide 6E.1 Transfer characteristics

Tuesday, October 22, 2002Slide 7E.1 f T versus geometry and temperature

Tuesday, October 22, 2002Slide 8E.1 Driver specifications 1.7 … 3.0 V p-p per side  Adjustable output amplitude 30% … 70%  Adjustable duty cycle –0.15 … –1.1 V  Adjustable output offset 50   On-chip terminated 2.8 W  DC power dissipation –5.2 V  Single-supply 0.5 …1.2 V p-p per side  Differential input data 3 V p-p per side  Differential output data

Tuesday, October 22, 2002Slide 9E.1 Circuit schematic

Tuesday, October 22, 2002Slide 10E.1 Gain block architecture

Tuesday, October 22, 2002Slide 11E.1 Distributed output stage

Tuesday, October 22, 2002Slide 12E.1 Control function implementation Pulse width controlOutput offset control

Tuesday, October 22, 2002Slide 13E.1 Chip microphotograph Fabricated by Fujitsu Quantum Devices Limited 0.15  m AlGaAs/InGaAs PHEMT process Substrate height of 28  m Single-metal layer with underpasses Through-wafer vias for grounding Schottky diodes Epitaxial resistors 3.99 mm 1.95 mm

Tuesday, October 22, 2002Slide 14E.1 Setup for on-wafer eye measurements Anritsu MP1801A 43.5G Mux 86100A scope & 83484A 50 GHz mod. 12” flexible 2.4 mm cables 65 GHz GGB MCW with 150  m pitch 20 dB attenuator 60” flexible 2.4 mm cable for clock sync.

Tuesday, October 22, 2002Slide 15E.1 Bandwidth of measurement setup BW = 16 GHz

Tuesday, October 22, 2002Slide 16E.1 40 Gb/s eye-diagram (test setup) T r = 12.7 ps T f = 11.9 ps T j = 6.7 ps

Tuesday, October 22, 2002Slide 17E.1 Nominal eye-diagrams 40 Gb/s44 Gb/s Output swing of 3.0 V p-p per side Rise/fall times are 10.9/11.4 ps Jitter is 8.6 ps (peak to peak)

Tuesday, October 22, 2002Slide 18E.1 Control features applied at 40 Gb/s Low amplitude Output swing of 1.7 V Maximum offset Offset of –1.2 V

Tuesday, October 22, 2002Slide 19E.1 Control features applied at 40 Gb/s 30% DCD66% DCD

Tuesday, October 22, 2002Slide 20E.1 Summary A full featured 3-V 40 Gb/s modulator driver has been designed and fabricated using a GaAs PHEMT process Limitations associated with the technology, particularly its low f T, can be overcome in design The design is very challenging because it involves a complex set of trade-offs The result is a unique and robust circuit that exhibits excellent yield and performance

Tuesday, October 22, 2002Slide 21E.1 Acknowledgment The authors would like to thank Fujitsu Quantum Devices Limited for fabricating the die They would also like to express their gratitude to Quake colleagues H. Tran and D. Viorel for their valuable contributions