February 12, 2009 Center for Hybrid and Embedded Software Systems Timing-aware Exceptions for a Precision Timed (PRET) Target Ben Lickly Hiren D. Patel PRET Philosophy The traditional abstractions used in computer systems only concern themselves with the “functional” aspects of a program. This allows the use of techniques like speculative execution, caches, interrupts, and dynamic compilation that offer improved average-case performance at the expense of predictable execution times. The PRET project aims to improve the timing predictability at all layers of abstraction by carefully reexamining and reworking various architectural and compiler advancements with an eye toward their effects on timing behavior and worst-case bounds.. Programming Models One of the models of computation that seems to fit very well with the PRET architecture is Giotto. Advantages: Time-triggered tasks map very well onto PRET hardware threads with timing instructions Leverage existing C code generation infrastructure of Ptolemy II to automatically synthesize PRET programs from Ptolemy’s Giotto models. Time-based Exceptions In some cases it may be necessary to specify what happens in case a timing requirement is not met. In these cases, we would like to specify exception handling code that will handle missed deadlines. We intend to to use the clang/LLVM compiler infrastructure as the base for our exception implementation. This is an open-source code base written with an emphasis for simplicity and extensibility. Relevant features include: Source code rewriting Static analysis Code generation for SPARC V8 References 1. Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel, Stephen A. Edwards and Edward A. Lee, Predictable Programming on a Precision Timed Architecture, in proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), October, Predictable Programming on a Precision Timed Architecture 2. Hiren D. Patel, Ben Lickly, Bas Burgers and Edward A. Lee, A Timing Requirements- Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture, Technical Report No. UCB/EECS , September, 2008.A Timing Requirements- Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture 3. Shanna-Shaye Forbes, Hugo A. Andrade, Hiren D. Patel and Edward A. Lee. An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture, In proceedings of the 12-th IEEE International Symposium on Distributed Simulation and Real Time Applications, (DSRT), October, 2008.An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture Acknowledgement This work was supported in part by the Center for Hybrid and Embedded Software Systems (CHESS) at UC Berkeley, which receives support from the National Science Foundation (NSF awards # (CSR-EHS:PRET) and # (CSR-CPS)), the U. S. Army Research Office (ARO#W911NF ), the U. S. Air Force Office of Scientific Research (MURI #FA ), the Air Force Research Lab (AFRL), the State of California Micro Program, and the following companies: Agilent, Bosch, HSBC, Lockheed-Martin, National Instruments, and Toyota. ISA Extensions The instruction-set architecture is augmented with timing instructions, which control the execution time of the sequence of assembly instructions that they surround. In the code to the right, the red deadline instructions specify the timing of the enclosed code. Even though the PRET project encompasses all the abstraction layers of a computer system, this poster primarily focuses on the middle layers, such as the instruction- set architecture, compilers and code generators, and specification languages.. Ptolemy II Code Generation clang/LLVM Compilation