Interconnect Characteristics of 2.5-D System Integration Scheme Yangdong (Steven) Deng & Wojciech P. Maly

Y. Deng & W. MalyPage 2 Interconnect Characteristics of 2.5-D System Integration Scheme Motivation  System-on-a-chip (monolithic integration)  Long wire delay dominates device delay  Mixed-technology design DRAM Cache Analog/RF RISC core PLL high performance logic random logic System-on-a-Chip

Y. Deng & W. MalyPage 3 Interconnect Characteristics of 2.5-D System Integration Scheme 2.5-D System Integration 2.5-D System random logic analog/RF circuit high performance logic CPU DRAM stacked cache  Technology and system co-design to achieve top performance  Potentials of 2.5-D System Integration  Allow optimum technology mix  Reduced chip area  Potential for top performance

Y. Deng & W. MalyPage 4 Interconnect Characteristics of 2.5-D System Integration Scheme Objective  Assess potential of 2.5-D system integration  Explore the solution space  Compare 2-D and 2.5-D integration schemes  Study the interconnection characteristics of 2.5-D Integration  Develop prototyping 2.5-D physical design algorithms  Formulation of problem  Implementation tradeoff

Y. Deng & W. MalyPage 5 Interconnect Characteristics of 2.5-D System Integration Scheme Approach  Coarse-grained approach – 2.5-D floorplanner  Fine-grained approach – 2.5-D standard cell placer  Conventional physical design tools for comparison floorplanning approach 2.5-D floorplan 2-D floorplan block-level netlist 2-D placement2.5-D placement gate-level netlist placement approach

Y. Deng & W. MalyPage 6 Interconnect Characteristics of 2.5-D System Integration Scheme 2.5-D Interconnection  Different 2.5-D interconnection technologies are being developed  2.5-D via is “expensive”  Fabricating cost  Consumed chip area  Optimizing wirelength using minimal number of 2.5-D vias 2.5-D Via 2.5-D System

Y. Deng & W. MalyPage 7 Interconnect Characteristics of 2.5-D System Integration Scheme  Bounded Slice-line Grid (BSG) 1 is a new floorplan representation  Maintain a BSG data structures for each die of 2.5-D system  Simulated annealing engine for optimization  New configuration: displacing, rotating, and swapping  Cost function: BSG Based 2.5-D Floorplanner 1 S. Nakatate, et al., Module Placement on BSG-Structure and IC layout Applications, ICCAD, 1996 c b a d x y x y b a c d WaWa WbWb WdWd WcWc T S

Y. Deng & W. MalyPage 8 Interconnect Characteristics of 2.5-D System Integration Scheme Floorplan of Benchmark Circuit AMI49 Monolithic Floorplan 2.5-D Floorplan B19 B7 B8 B9 B28 B11 B1 B32 B21 B0 B2 B27 B26 B24 B4 B13 B16 B23 B12 B5 B20 B15 B31 B14 B22 B3 B10 B25 B17 B30 B29 B18 B6 Net 31 B19 B3 B7 B14 B8 B29 B10 B30 B1 B32 B9 B24 B23 B5 B21 B12 B22 B D via B28 B11 B17 B18 B6 B26 B31 B27 B16 B20 B4 B2 B0 B25 B13

Y. Deng & W. MalyPage 9 Interconnect Characteristics of 2.5-D System Integration Scheme Results of Floorplanning  ami33 (33 modules, 123 nets) 2-D Floorplan 2.5-D Floorplan Reduction Total Area 1, 316, 140 1, 282, 330 3% Longest Wire Length 2, 923 2, 688 8% Total Wire Length 81, , % 2-D Floorplan 2.5-D Floorplan Reduction Total Area 44, 096, , 200, 556 2% Longest Wire Length 12, 005 8, % Total Wire Length 894, , %  ami49 (49 modules, 409 nets)

Y. Deng & W. MalyPage 10 Interconnect Characteristics of 2.5-D System Integration Scheme Min-Cut Bipartition 2.5-D Placer  Adapted from UCLA Capo placer  Netlist is first bi-partitioned by the multi-level partitioning engine  Iteratively place two sub-netlists

Y. Deng & W. MalyPage 11 Interconnect Characteristics of 2.5-D System Integration Scheme Wire Length  Average 16% total wire length reduction  Average 29% worst-case wire length reduction Design

Y. Deng & W. MalyPage 12 Interconnect Characteristics of 2.5-D System Integration Scheme Wire Length Distribution micron Reduced Power Improved Timing Scaled Local Nets Number of Wires

Y. Deng & W. MalyPage 13 Interconnect Characteristics of 2.5-D System Integration Scheme Conclusion  2.5-D physical design tools  2.5-D floorplanner and 2.5-D standard cell placer  2.5-D integration scheme offers significant advantages  Reduced wire length  Improved timing and reduced power consumption  Reduced chip area

Y. Deng & W. MalyPage 14 Interconnect Characteristics of 2.5-D System Integration Scheme Subsequent Research  Industrial size designs to assess 2.5-D integration  Routability assessment of 2.5-D placement  Complete 2.5-D design flow  Refined 2.5-D physical design algorithms  Floorplan, placement, routing, …  Clock and power distribution in 2.5-D system  …