CSc 352 An Introduction to make Saumya Debray Dept. of Computer Science The University of Arizona, Tucson

Structuring large applications So far, all of our programs have involved a single source file – obviously impractical for large(r) programs – even where practical, may not be good from a design perspective If an application is broken up into multiple files, we need to manage the build process: – how do we (re)compile the various different files that make up the application? 2

Structuring large applications When one file is edited, other files may need to be recompiled – changes to typedefs or macros in header files – changes to types of shared variables Applications can contain a lot of files – E.g.: Linux kernel source code:  4,900 files Recompiling all files whenever any file is changed can be very time-consuming. 3

Structuring large applications Obvious idea: only recompile those files that need to be recompiled. 4

Structuring large applications Obvious idea: only recompile those files that may be affected by a change. 5 changed affected

Structuring large applications “Smart recompilation” : issues – need to be able to express, keep track of dependencies between files “dependency”  which files are (might be) affected by a change to a file? – need to make sure that all (and only) affected files are recompiled doing this manually is tedious and error-prone want an automated solution make: a tool to automate recompilation of parts of a project based on a file of dependencies (“make file”) 6

Digression: compiling multi-file programs 7 file1.c gcc OPTS -c file1.o file2.c gcc OPTS -c fileN.cfileN.o file2.o … gcc executable

Digression: compiling multi-file programs 8 file1.c gcc OPTS -c file1.o file2.c gcc OPTS -c fileN.cfileN.o file2.o … gcc executable source files Only one of these files contains main()

Digression: compiling multi-file programs 9 file1.c gcc OPTS -c file1.o file2.c gcc OPTS -c fileN.cfileN.o file2.o … gcc executable object files machine code, but not executable

Digression: compiling multi-file programs 10 file1.c gcc OPTS -c file1.o file2.c gcc OPTS -c fileN.cfileN.o file2.o … gcc executable linker invocation combines various *.o files together

Digression: compiling multi-file programs 11 file1.c gcc OPTS -c file1.o file2.c gcc OPTS -c fileN.cfileN.o file2.o … gcc executable gcc -c compile to a linkable object don’t worry about main()

make files make files specify: – dependencies between files – how to update dependent files 12

make files make files specify: – dependencies between files – how to update dependent files 13 dependency how to update the dependent file to satisfy this dependency

make files make files specify: – dependencies between files – how to update dependent files 14 dependency how to update the dependent file to satisfy this dependency

make files: structure Structure of a make file: Macros (optional) target … : prerequisites … command \t (tab) target: (usually) the name of a file that is created by a program prerequisite: a file used as input to create the target rule command: an action carried out by make to (re)construct target

make files: an elementary example Dependency structure: make file: 16 spellcheck.c spellcheck.h spellcheck include compiledependencies spellcheck: spellcheck.c spellcheck.h gcc –Wall spellcheck.c must be a tab!

make files: an elementary example Dependency structure: 17 spellcheck.c spellcheck.h spellcheck include compiledependencies why is this not a dependency?

make files: example 2 file1.o : file1.c hdrfile1.h gcc -Wall -g -c file1.c file2.o : file2.c hdrfile1.h hdrfile2.h gcc -Wall -g -c file2.c execFile : file1.o file2.o gcc file1.o file2.o -o execFile 18

make files: Macros Makes make files easier to write, modify – define: Name = replacement list – use: $(Name) Example: 19 CC = gcc OPTLEV = –O2 # optimization level CFLAGS = –Wall –g –D DEBUG $(OPTLEV) – c... file1.o : file1.c hdrfile1.h $(CC) $(CFLAGS) file1.c

Internal Macros These are macros that are predefined in make. – Examples: CC = cc CXX = g++ LD = ld Execute “make –p” to get a complete list – Unix environment variables are inherited by make as predefined macros execute “printenv” to get a complete list 20

Using make Invocation: make [ -f makeFileName ] [ target ] 21 default: make searches (in order) for: makefile Makefile default: builds the first target in the make file

How make works When invoked, begins processing the appropriate target For each target, considers the prerequisites it depends on: target : file 1 file 2 … – checks (recursively) whether each of file i (1) exists and (2) is more recent than the files that file i depends on; if not, executes the associated command(s) to update file i – checks whether target exists and is more recent that file i if not, executes the commands associated with target 22

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g Dependence structure 23 file a file b file c file e file d file f file g cmd d

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g make execution 24 file a file b file c file e file d file f file g current? changed cmd d

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g make execution 25 file a file b file c file e file d file f file g current? changed current? cmd d

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g make execution 26 file a file b file c file e file d file f file g current? changed current? cmd d

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g make execution 27 file a file b file c file e file d file f file g current? changed current? ok cmd d

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g make execution 28 file a file b file c file e file d file f file g current? changed current? update! cmd d

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g make execution 29 file a file b file c file e file d file f file g current? changed current? update! cmd d

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g make execution 30 file a file b file c file e file d file f file g current? changed update! cmd d

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g make execution 31 file a file b file c file e file d file f file g changed update! cmd d

How make works Make file file a : file b file c cmd a file b : file e file d cmd b file c : file d file f cmd c file d : file f file g make execution 32 file a file b file c file e file d file f file g changed cmd d

Phony Targets A phony target is one that is not the name of a file, e.g.: “make clean” will remove a.out and *.o files 33 phony target clean: rm –f *.o a.out

Phony Targets This won’t work if we (accidentally) create a file named “clean” Fix:.PHONY: clean clean: rm *.o a.out 34 clean: rm –f *.o a.out cleanup actions will be executed even if there is a file named “clean”

Command execution 35 Commands to update a target are executed by invoking a new subshell for each command line – invoking commands like “cd” on one command line won’t affect other command lines – to have one command affect the next, put them on the same line, e.g.: cd targetDir ; cmd If a command returns an error (nonzero exit status), make abandons that rule ― to ignore errors in a command, precede with ‘-’

Command execution 36 The shell used is given by the macro SHELL – defaults to /bin/sh [Ubuntu]: /bin/sh points to dash, a stripped-down version of bash – to use a different shell, define SHELL appropriately, e.g.: SHELL = /bin/csh

Telling make how to process files Suffix Rules: Structure:.suf1.suf2: recipe Example:.c.o: … 37 Pattern Rules: Structure: %.suf2 : %.suf1 recipe Example: %.c : %.o: … To create a file foo.suf2 from foo.suf1, execute recipe (suf1 comes before suf2: confusing ) Need a way to refer to a particular C file “compile this file in this way…”

Special Macros These are macros defined internally for each dependency line: 38 name of current target $*basename of current target (i.e., target without its file extension) $<(inference rules) the single prerequisite that causes execution of the rule $?list of all prerequisites newer than target Example:.dvi.ps: dvips $< -o $*.ps describes how to create a.ps file from a.dvi file.

Gnu Make String Functions General syntax: $(funcName args)or${funcName args} Most useful for us: – $(subst fromStr, toStr, txtStr ) returns the result of replacing each occurrence of fromStr by toStr in txtStr – $(patsubst pattern, replacement, txtStr ) finds whitespace-separated words in txtStr that match pattern and replaces them with replacement. “%” can be used as a wildcard. – $( var : suffix = replacement ) replaces suffix at the end of filenames in var by replacement 39

Examples Goal: convert PDF files to HTML using pdftohtml 40 Suffix rules:.pdf.html: pdftohtml $< subst: PDFS = file1.pdf file2.pdf file3.pdf HTMLS = $(subst.pdf,.html,$(PDFS)) all : $(HTMLS) pdftohtml $< patsubst: PDFS = file1.pdf file2.pdf file3.pdf HTMLS = $(patsubst %.pdf,%.html,$(PDFS)) all : $(HTMLS) pdftohtml $< Suffix replacement: PDFS = file1.pdf file2.pdf file3.pdf HTMLS = $(PDFS:pdf=html) all : $(HTMLS) pdftohtml $<

Topics not covered make has a lot of functionality we won’t get to cover, e.g.: – implicit rules – implicit variables – conditional parts of make files – recursively running make in subdirectories See online make tutorials for more information 41