STT-RAM Generator - Anurag Nigam.

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Presentation transcript:

STT-RAM Generator - Anurag Nigam

Motivation Challenges in SRAM Solution High Leakage Leakage current Challenges in SRAM High Leakage Solution Non-volatile memory

Memory Technology Comparison

STT-RAM bit cell overview MTJ WL SL BL Oxide layer Free Ferro magnetic layer RP RAP Hard Ferro magnetic layer MTJ 1 MTJ 1 access transistor

Bit-cell Design IMTJ = f (Vin, parameters) Behavioral current source Need to solve differential equation How to solve differential equation ??

Capacitor current equation V I = C dV/dt

Bit-cell design Editing CDF parameter to create behavioral source componentName = isource I = f(V) Editing CDF parameter to create behavioral source

Bit-cell design Write “1” Operation WL BL=0V SL=1V Switching Schematic

Memory Interface STT-RAM Macro R’/W Write Driver Timing Block Sensing Block Memory Array WLen SAen CLK Data In Data Out R/W ADDR CL WLS R’/W STT-RAM Macro

Write Driver TBUF BL SL Write “1”  BL =0 SL=1 Write “0”  BL=1 SL=0

Sense amplifier design Test bit-cell

R-V characteristic of MTJ RAP RP Two states (RAP and RP) Resistance is a function of voltage

Schematic automation Leaf-cell schematic creation Bitcells – Manual (using current/voltage sources) Decoders – Skill Sense amp. Timing block, Write driver – Manual Memory array creation 1Kb array - Skill

Schematic automation Decoder Write Driver Memory Array procedure(Create7to128DecoderSchematic(libname,cellname)) Write Driver procedure(CreateWriteDrSchematic(libname,cellname,C)) Memory Array procedure(CreateSTTRAMSchematic(libname,cellname,R,C))

1Kb STT-RAM array 128 x 8 array Write Driver Timing block Sense amplifier

Read and Write operation clk Data<0> Out<0> Write “1” Read “1” Write “0” Read ”0”

Deliverables STT-RAM bit-cell SPICE model Skill script to generate complete functional STT-RAM Class-specific work Importing bit-cell model in ADE Skill script development

Thanks for your time !