Semiconductor Device Modeling and Characterization – EE5342 Lecture 10– Spring 2011 Professor Ronald L. Carter
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©rlc L10-16Feb20114 Additional University Closure Means More Schedule Changes Plan to meet until noon some days in the next few weeks. This way we will make up for the lost time. The first extended class will be Monday, 2/14. The MT changed to Friday 2/18 The P1 test changed to Friday 3/11. The P2 test is still Wednesday 4/13 The Final is still Wednesday 5/11.
MT and P1 Assignment on Friday, 2/18/11 Quizzes and tests are open book –must have a legally obtained copy-no Xerox copies. –OR one handwritten page of notes. –Calculator allowed. A cover sheet will be published by Wednesday, 2/16/11. ©rlc L10-16Feb20115
6 Ideal Junction Theory Assumptions E x = 0 in the chg neutral reg. (CNR) MB statistics are applicable Neglect gen/rec in depl reg (DR) Low level injections apply so that n p < p po for -x pc < x < -x p, and p n < n no for x n < x < x nc Steady State conditions
©rlc L10-16Feb20117 Forward Bias Energy Bands EvEv EcEc E Fi xnxn x nc -x pc -x p 0 q(V bi -V a ) E FP E FN qV a x Imref, E Fn Imref, E Fp
©rlc L10-16Feb20118 Law of the junction (follow the min. carr.)
©rlc L10-16Feb20119 Law of the junction (cont.)
©rlc L10-16Feb Law of the junction (cont.)
©rlc L10-16Feb Injection Conditions
©rlc L10-16Feb Ideal Junction Theory (cont.) Apply the Continuity Eqn in CNR
©rlc L10-16Feb Ideal Junction Theory (cont.)
©rlc L10-16Feb Ideal Junction Theory (cont.)
©rlc L10-16Feb Excess minority carrier distr fctn
©rlc L10-16Feb Carrier Injection -x p xnxn -x pc 0 ln(carrier conc) ln N a ln N d ln n i ln n i 2 /N d ln n i 2 /N a x nc x ~V a /V t
©rlc L10-16Feb Minority carrier currents
©rlc L10-16Feb Evaluating the diode current
©rlc L10-16Feb Special cases for the diode current
©rlc L10-16Feb Ideal diode equation Assumptions: –low-level injection –Maxwell Boltzman statistics –Depletion approximation –Neglect gen/rec effects in DR –Steady-state solution only Current dens, J x = J s expd(V a /V t ) –where expd(x) = [exp(x) -1]
©rlc L10-16Feb Ideal diode equation (cont.) J s = J s,p + J s,n = hole curr + ele curr J s,p = qn i 2 D p coth(W n /L p )/(N d L p ) = qn i 2 D p /(N d W n ), W n > L p, “long” J s,n = qn i 2 D n coth(W p /L n )/(N a L n ) = qn i 2 D n /(N a W p ), W p > L n, “long” J s,n > N d
©rlc L10-16Feb Diffnt’l, one-sided diode conductance VaVa IDID Static (steady- state) diode I-V characteristic VQVQ IQIQ
©rlc L10-16Feb Diffnt’l, one-sided diode cond. (cont.)
©rlc L10-16Feb Charge distr in a (1- sided) short diode Assume N d << N a The sinh (see L12) excess minority carrier distribution becomes linear for W n << L p p n (x n )=p n0 expd(V a /V t ) Total chg = Q’ p = Q’ p = q p n (x n )W n /2 xnxn x x nc p n (x n ) W n = x nc - x n Q’ p pnpn
©rlc L10-16Feb Charge distr in a 1- sided short diode Assume Quasi-static charge distributions Q’ p = Q’ p = q p n (x n )W n /2 d p n (x n ) = (W/2)* { p n (x n,V a + V) - p n (x n,V a )} xnxn x x nc p n (x n,V a ) Q’ p pnpn p n (x n,V a + V) Q’ p
©rlc L10-16Feb Cap. of a (1-sided) short diode (cont.)
©rlc L10-16Feb General time- constant
©rlc L10-16Feb General time- constant (cont.)
©rlc L10-16Feb General time- constant (cont.)
©rlc L10-16Feb References *Fundamentals of Semiconductor Theory and Device Physics, by Shyh Wang, Prentice Hall, **Semiconductor Physics & Devices, by Donald A. Neamen, 2nd ed., Irwin, Chicago. M&K = Device Electronics for Integrated Circuits, 3rd ed., by Richard S. Muller, Theodore I. Kamins, and Mansun Chan, John Wiley and Sons, New York, Device Electronics for Integrated Circuits, 2 ed., by Muller and Kamins, Wiley, New York, Physics of Semiconductor Devices, by S. M. Sze, Wiley, New York, Physics of Semiconductor Devices, Shur, Prentice- Hall, 1990.