SMALL SIGNAL FET (Field– Effect Transistors) AMPLIFIER 1.Introduction/Basic 2.FET Small-Signal Model 3.Fixed-Bias Configuration 4.Self-Bias Configuration 5.Voltage-Divider Configuration 6.Common-Drain Configuration 7.Common-Gate Configuration

1.INTRODUCTION / BASIC

Field–Effect Transistors (FET) FET’s (Field – Effect Transistors) are much like BJT’s (Bipolar Junction Transistors). FET is usually called a unipolar transistor being that the current carrier is wholly of a single type either electron or holes only. While the bipolar transistor is a dual current carrier system having both electrons and holes together. Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FET’s are voltage controlled devices whereas BJT’s are current controlled devices. FET’s also have a higher input impedance, but BJT’s have higher gains. FET’s are less sensitive to temperature variations and because of there construction they are more easily integrated on IC’s. FET’s are also generally more static sensitive than BJT’s.

FET Types JFET ~ Junction Field-Effect Transistor MOSFET ~ Metal-Oxide Field-Effect Transistor - D-MOSFET ~ Depletion MOSFET - E-MOSFET ~ Enhancement MOSFET

Bipolar Junction Transistors Transistor Construction There are two types of transistors: pnp and npn-type. Note: the labeling of the transistor: E - Emitter B - Base C - Collector

JFET Construction There are two types of JFET’s: n-channel and p-channel. The n-channel is more widely used. There are three terminals: Drain (D) and Source (S) Gate (G) n

Basic Operation of JFET JFET operation can be compared to a water spigot: The source of water pressure – accumulated electrons at the negative pole of the applied voltage from Drain to Source The drain of water – electron deficiency (or holes) at the positive pole of the applied voltage from Drain to Source. The control of flow of water – Gate voltage that controls the width of the n-channel, which in turn controls the flow of electrons in the n-channel from source to drain.

JFET Operating Characteristics There are three basic operating conditions for a JFET: A.V GS = 0, V DS increasing to some positive value B.V GS < 0, V DS at some positive value C.Voltage-Controlled Resistor

JFET Symbols n-channel p-channel

Common JFET Biasing Circuits General Relationships The general relationships that can be applied to dc analysis of all FET amplifiers are: Shockley’s equation is applied to relate the input and output quantities: Pinch-off

Fixed-Bias Configuration Fixed-bias configurationNetwork for dc analysis V GS = - V GG V DS = V DD – I D R D V S = 0 V D = V DS V G = V GS

Plotting the Transfer Curve From Shockley’s equation, I DSS and Vp (V GS(off) ), the Transfer Curve can be plotted using these 3 steps: Step 1: Solving for V GS = 0V: Step 2: Solving for V GS = Vp (V GS(off) ): Step 3: Solving for V GS = 0V to Vp:

Fixed-Bias Transfer Curve Plotting shockley’s equation Finding the solution for the fixed-bias configuration Shorthand Method V GS versus I D using Shockley’s equation V GS I D 0I DSS 0.3 V P I DSS /2 0.5 V P I DSS /4 V P 0 mA

Example 1: Determine : V GS Q, I D Q, V DS, V D, V G and V S

Graphical solution for the network

Self-Bias Configuration JFET self-bias configurationDC analysis of the self-bias configuration

Self-Bias Calculations For the indicated loop: To solve this equation select an I D < I DSS and use the component value for R S. Plot this point: I D and V GS and draw a line from the origin of the axis to this point. Next plot the transfer curve using I DSS and V P (V P = V GSoff in specification sheets) and a few points such as I D = I DSS /4 and I D = I DSS /2 etc. Where the first line intersects the transfer curve is the Q-point. Use the value of I D at the Q-point (I DQ ) to solve for the other voltages:

Defining a point on the self-bias line. Self-Bias Transfer Curve

Sketching the self-bias line. Self-Bias Transfer Curve

Example 6.2

Sketching the self-bias line for the network

Sketching the device characteristics for the JFET

Determining the Q-point for the network

Determining the quiescent point of operation for the network of Example 2.

Example 3

Example 4

Sketching the dc equivalent of the network

Voltage-Divider Bias I G = 0A in FETs. Unlike BJTs, where I B affected I C ; in FETs it is V GS that controls I D.

Voltage-Divider Bias Calculations Using Kirchoff’s Law: Rearranging and using I D =I S : Again the Q point needs to be established by plotting a line that intersects the transfer curve.

Voltage-Divider Q-point 1.Plot the line: By plotting two points: V GS = V G, I D =0 and V GS = 0, I D = V G /R S 2.Plot the transfer curve by plotting I DSS, V P and calculated values of I D. 3.Where the line intersects the transfer curve is the Q point for the circuit.

Voltage-Divider Bias Calculations Using the value of ID at the Q-point, solve for the other variables in the Voltage-Divider Bias circuit:

Example 5

Determining the Q-point for the network

Example 6

Determining the network equation for the configuration

Determining the Q-point for the network

Summary Table

P-Channel FETs For p-channel FETs the same calculations and graphs are used, except that the voltage polarities and current directions are the opposite. The graphs will be mirrors of the n- channel graphs.

Practical Applications Voltage-Controlled Resistor JFET Voltmeter Timer Network Fiber Optic Circuitry