ECE 545 Project 1 Introduction & Specification Part I

Cipher Message / Ciphertext Ciphertext / Message Cryptographic Key m bits k bits Encrypt/Decrypt 1 bit

Secret-Key Ciphers key of Alice and Bob - K AB Alice Bob Network Encryption Decryption

Block vs. stream ciphers Stream cipher memory Block cipher KK M 1, M 2, …, M n m 1, m 2, …, m n C 1, C 2, …, C n c 1, c 2, …, c n C i =f K (M i )C i = f K (m i, m i-1, …, m 2, m 1 ) Every block of ciphertext is a function of only one corresponding block of plaintext Every block of ciphertext is a function of the current and all proceeding blocks of plaintext

Initial transformation Final transformation r times Round Key[i] i:=i+1 Round Key[0] i:=1 i < r Cipher Round Round Key[#rounds+1] Typical Flow Diagram of a Secret-Key Block Cipher

register combinational logic one round multiplexer Basic iterative architecture round key Encrypt/Decrypt

IN OUT M1 C1 M2 C2 M3 Basic architecture: Timing r · clock_period CLK

RC5 Ron Rivest, MIT, 1994 variable key length - k variable i/o block size - m variable number of rounds - r simple description (Ron’s Code 5, Rivest’s Cipher 5)

One of the fastest ciphers Basic operation Y Y<<X Rotation by a variable number of bits RC5 X times

RC5 w/r/b w - word size in bits input/output block size, m = 2 words = 2  w bits Typical values: w=32  64-bit input/output block w=64  128-bit input/output block r - number of rounds b - key size in bytes key size in bits, k = 8  b bits 0  b  255 w = 16, 32, 64

RC5 32/12/16 64 bit block 12 rounds 128 bit key Most commonly used sets of parameters RC5 64/20/ bit block 20 rounds 256 bit key

Encryption A || B = M A = A + S[0] B = B + S[1] for i= 1 to r do { A= (A  B) <<< B + S[2i] B= (B  A) <<< A + S[2i+1] } C= A || B RC5 Decryption A || B = C for i= r downto 1 do { B= ((B  S[2i+1]) >>> A)  A A= ((A  S[2i])>>>B)  B } B = B  S[1] A = A  S[0] M= A || B

Notation || - concatenation  - XOR X <<< Y - X rotated by Y positions + - addition without carry (addition modulo 2 w ) S[i] – value of a round key i

variable rotation ROL32 Mux-based rotation High-speed clock C ASM Variable Rotation A <<< B ROL A, B C = (A > (32-B)); min (B, 32-B) CLK’ cycles Hardware Software fast clock CLK’ A A<<<B A<<<0A<<<16 32 B[4] B[3] B[2] B[1] B[0]

RC5 - Key Scheduling k bits of the main key 2  r + 2 round keys = (2  r + 2 )  w bits Two magic constants: P w = Odd ((e-2)  2 w ) Q w = Odd ((  -1)  2 w ) e - base of natural logarithms e =  - golden ratio = yx-y x x y = y =

RC5 - Key Scheduling Initialize Mix t = 2  r + 2 c = 8b8b w S[0] = P w for i=0 to t-1 do S[i] = S[i] + Q w i = j = 0 A = B = 0 do 3  max{t, c} times { A = S[i] = (S[i] + A + B) <<< 3 B = L[j] = (L[j] + A + B) <<< (A+B) i = (i+1) mod t j = (j+1) mod c }

key scheduling encryption/decryption memory of round keys output input input interface output interface Control unit control Implementation of a secret-key cipher Round keys precomputed key

Encryption/decryption unit clock reset encrypt/decrypt data input data available data read m key input key available key read k Key scheduling unit Key memory data output write full n round key(s) round number round key(s) cycle number

Project 1 - Organization 25 points total 4 phases, 1 phase per week grading 5 points for each phase + 5 point for a final report individual project the same for all students contest for the best results (bonus points awarded to winners)

Project 1 – Honor Code Rules All students are expected to write and debug their codes individually Students are encouraged to help and support each other in all problems related to the - operation of the CAD tools, - basic understanding of the problem.

Project 1 – Optimization Criteria Maximum ratio Encryption/Decryption Throughput divided by Total Circuit Area

Primary parameters of hardware implementations for secret-key block ciphers Latency Throughput Encryption/ decryption Time to encrypt/decrypt a single block of data MiMi CiCi Number of bits encrypted/decrypted in a unit of time Encryption/ decryption MiMi M i+1 M i+2 CiCi C i+1 C i+2 Throughput = Block_size · Number_of_blocks_processed_simultaneously Latency

Project 1 - Organization Electronic submission by Monday, noon Feedback provided to students in class and during office hours

Project 1 – Platform & tools Target devices: Xilinx FPGA Spartan 2 family Tools: VHDL Simulation: Aldec Active HDL or ModelSim VHDL Synthesis: Synplify Pro Implementation: Xilinx ISE

Phase 1, due Monday October 4, noon 1.Draw a block diagram of a single round of encryption 2.Draw a block diagram of a single round of decryption 3.Draw a combined block diagram of a circuit capable of implementing a single round of both encryption and decryption with possible resource sharing 4.Describe in VHDL combinational logic implementing one round of encryption and decryption using dataflow design style, i.e., using only concurrent statements 5. Write a testbench capable of verifying function of your circuit 6. Describe the entire datapath of the encryption/decryption unit in VHDL, assuming the use of the basic iterative architecture