March 14, 2016 Report on SMU R&D work1 Link-On-Chip (LOC) 1st Prototype  Status:  Prototype chip with the clock unit (PLL), serializer, laser driver, designed and submitted in Feb Chip will be back to SMU in May  One self-biasing PLL (1.25GHz), one LC PLL (4GHz) are also placed on this chip for irradiation tests.  Goal:  Evaluate the LOC design, perform in-lab tests, and rad-hard tests at system level.  Provide a test chip to work on fiber attachment at chip level.  Spec:  2.5 Gbps.  Plan:  2007: Summer, in-lab test; Fall, irradiation test.  Fiber attachment schemes test.  LOC2 design. LOC2 is aimed at a complete serializer chip of 2.5 to Gbps data rate. Need to talk to “users” about input I/O definition. Aim at a submission in Spring 2008.

March 14, 2016 Report on SMU R&D work2 GOL Test up to 100 Mrad  Test with 230 MeV proton beam  TID: survived 106 Mrad (Si) without current increase. Chip fully functioning during and after irradiation.  SEE: no error when flux < 1×10 9 proton/cm 2 /sec. When flux = 5×10 11 proton/cm 2 /sec, error cross section is measured to be 1.1× error·cm 2 /proton (loss of link) and 1.1× error·cm 2 /proton (bit error).  Jitter: Complies with the modified (1.6Gbps vs 1.25 Gbps) IEEE Gigabit Ethernet standards. Before irradiationAfter irradiation Jitter ComponentsTx clkSerial DataTx clkSerial Data Random (RMS)10.2ps4.6ps11.1ps4.7ps Deterministic (Pk-Pk) 67.6ps55.6ps67.0ps57.9ps

March 14, 2016 Report on SMU R&D work3 Silicon-On-Sapphire (SOS) 0.25  m Technology Evaluation  Goal: to evaluate the 0.25  m SOS technology for rad-hard ASIC design.  Advantages:  Low power, low cross talk, good for mixed signal ASIC design.  Economical for small to medium scale ASIC development. A multi-project run of 3×3 mm 2 for 100+ chips cost ~$35k.  Test chip fabricated:  8×12 transistors array with different layouts to study TID effects.  Shift registers to study SEE.  Other test structures: VCOs, Ring Oscillators, etc, for other studies.  TID with gamma (Co-60) up to 4 Mrad:  With a grounding plate under the chip during irradiation, there is no measurable leakage current and threshold voltage change in both NMOS and PMOS.  We postulate a mechanism that under the influence of the back plate potential, the migration of radiation induced electron-hole pairs is altered such that there is a dynamic balance of net charges in the substrate to be zero. Further studies with GEANT are being carried out.  SEE with 230 MeV proton beam:  With a total fluence of 1.9×10 13 proton/cm 2 and ionizing dose of 106 Mrad (Si), and a flux range from 1×10 7 to 5×10 11 proton/cm 2 /sec, no SEE was measured and all shift registers function after the irradiation.  Conclusion:  SOS 0.25  m technology is rad-hard for ATLAS inner detector readout upgrade ASIC development. No special layout technique (ELT, guard ring) is needed.  Propose:  We propose that this SOS 0.25  m technology be considered for LHC upgrade ASIC development. We welcome collaborations.

March 14, 2016 Report on SMU R&D work4 Fiber  The Fiber:  Infinicor SX+ 50/250  m/1.6mm MM 10G fiber from Corning. Germanium doped.  Test condition:  Gamma from Co-60.  Proton, 230 MeV, fluence: 1.9×10 13 proton/cm 2.  Results:  Two fiber tested.  Very small light loss at low flux. Big loss at high flux but anneals very quickly (within 1 hour) back.  Very promising for LHC upgrade.  Plan:  More tests with gamma.

March 14, 2016 Report on SMU R&D work5 VCSEL  The VCSEL:  HFE (10G LC w/ 50 ohm flex) from Finisar.  Test condition:  Irradiated with 230 MeV proton with a total fluence of 1.9×10 13 proton/cm 2.  The VCSELs are biased during irradiations.  Results:  Two VCSELs tested.  Eye diagram – see plots and table.  Looks very promising but more tests needed. VCSEL Before irradiationAfter irradiation Rise/fall time (ps) O-power (  W) Rise/fall time (ps) O-power (  W) L1 114/ / L2 120/ / L1, before irradiation L1, after irradiation