EE3A1 Computer Hardware and Digital Design Lecture 1 The Role of Hardware Description Languages

Syllabus  14 lectures u Design processes (1 and 10) u VHDL (2-6) u Digital integrated circuits (7 and 9) u Computer systems (8) u Microprocessor hardware (10-12) u System testing (13-14)  3 worked example classes u Last year’s exam  5 lab sessions

Assessment  75% exam in May/June u 1½ hours. Answer 2 out of 3 questions  25% coursework assignment u Use VHDL to design part of a microprocessor u January deadline

Introduction: Modern Digital Design  Modern technique for hardware design: u Hardware description languages HDLs u Write HDL description of what whole design does u Automatically translate into detailed hardware design: synthesis  Why is this good …

What’s wrong with traditional methods?  An example: Design a 4-bit comparator  When a>b then g=1; otherwise g=0.  2 different design teams work independently.

Solution from team 1  K-map?  8 inputs: K-map is difficult  Find another way

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb.  a=1000  b=0100  a is bigger

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb.  a=0100  b=1000  b is bigger

 Compare one bit at a time, starting from msb.  a=0100  b=0110 Solution 1: Idea to make it easy  Inconclusive: look at next bits  b is bigger

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb. Stage 3 a3a3 b3b3 g2g2 g

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb. Stage 3 a3a3 b3b3 g2g2 g a 3 is bigger: output a 1

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb. Stage 3 a3a3 b3b3 g2g2 g a 3 is smaller: output a 0

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb. Stage 3 a3a3 b3b3 g2g2 g Inconclusive: copy g 2 to output

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb.

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb.  Stage 2  Process is same as stage 3

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb.  Stage 1  Process is same as stage 2

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb. Stage 0 a0a0 b0b0 g0g

Solution 1: Idea to make it easy  Compare one bit at a time, starting from msb.

Solution 1: Final design

Solution from team 2  Subtract a from b.  If the answer is negative, a is bigger  The msb is sign bit  If b>a then b-a is positive, msb=0  If b<a then b-a is negative, msb=1  g = msb of ( b + (2’s complement of a) )

Solution 1: Idea to make it easy  g = msb of ( b + (2’s complement of a) )  Now we just need to build an adder

Solution 2: 1-bit adder xyC inSumC out

Solution 2: 1-bit adder  Standard circuit: look it up in a book

Solution from team 2  4 full adders chain together to give 4 bit adder:

Evaluation of 2 rival solutions

Evaluation  Design effort: Lot of work for a small design  Maintainability: Gate diagrams hard to understand  Both designs are quite poor  Need something quicker and easier

Evaluation  Which of the two designs is best? u What does best mean? u Cheapest? u Fastest? u Longest battery life? u What type of hardware will be used to build the design?  Probably don’t know answers yet.

Evaluation  Some types of hardware don’t use basic logic gates  FPGAs don’t use AND gate and OR gates.  Lot of effort was wasted  Avoid designing at level of logic gates.

Evaluation  The really big problem… u Designs don’t do the same thing! u a=1111 and b=0001 u Design 1 gives g=1 u Design 2 gives g=0  Why?

Evaluation of 2 rival solutions  a=1111 and b=0001  Design 1 gives g=1  Design 2 gives g=0  Why?

Number systems Unsigned Signed 2s complement  a=1111 and b=0001  Design 1 gives g=1  Design 2 gives g=0  No one was wrong  Spec was ambiguous  Outcome is disaster

Number systems  No one was wrong  Spec was ambiguous  Outcome is disaster

Wish list  No gate level designs. u Just say what we want design to do. u Gates generated automatically.  Specifications that have no ambiguity  Specifications that can be thoroughly tested in simulation  HDLs try to solve this

HDLs  VHDL: u g b else ‘0’;  Verilog: u assign g = a>b ? 1 : 0;

Types of description  Behavioural u says what it does u doesn’t say how to make it  g b else ‘0’;  Structural u says how to make it (connecting blocks together) u doesn’t say what it does

Questions  What type of description?  It can't be bargained with. It can't be reasoned with. It can’t show feel pity, or remorse, or fear. And it absolutely will not stop, ever, until you are dead.

Questions  What type of description?  The foot bone's connected to the shin bone, The shin bone's connected to the knee bone, The knee bone's connected to the thigh bone, The thigh bone's connected to the hip bone, The hip bone's connected to the back bone, The back bone's connected to the neck bone, The neck bone's connected to the head bone,

Shin Thigh Knee Hip Questions  What type of description?  The foot bone's connected to the shin bone, The shin bone's connected to the knee bone, The knee bone's connected to the thigh bone, The thigh bone's connected to the hip bone, The hip bone's connected to the back bone, The back bone's connected to the neck bone, The neck bone's connected to the head bone,

Structural descriptions: Netlists  Structural: u How to connect simpler units together u But we then need to design the simpler units

Structural descriptions: Netlists  Structural: u How to connect simpler units together u But we then need to design the simpler units  Netlist: u Special case of Structural u The only units used are already available

Computer Design Tools  Synthesis u Start with behavioural description u Know what it does u Synthesis generates a netlist to make it  Simulation u Take a description (behavioural or structural) u Apply inputs to it u Simulator predicts what outputs would be

Summary  Traditional methods u Productivity is too low. u Detailed decisions made early in design process. u Re-targetting from one technology to another means whole design must be repeated. u Specification may be ambiguous or incomplete.

Summary  HDLs aim to alleviate these problems.  Say what the modules of the design should do: u Behavioural description  Automatically translated to implementation: u Synthesis