Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F High-Speed and Low-Power Asynchronous SRAMs With On-Chip ECC to Improve System Reliability New Product Introduction: 16Mb Asynchronous SRAM with ECC ECC = Error-Correcting Code

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F Modern systems cannot tolerate bit errors in SRAMs Advanced computing systems require reliable high-speed SRAMs as control stores 1 memories Battery-backed systems require reliable low-power SRAMs to store critical data Soft Errors 2 corrupt memory content, resulting in a loss of critical data Error detection and correction is required to ensure data reliability Today’s systems require reliable high-speed and low-power SRAMs with error detection and correction Multi-Function Printer by Canon Router by Cisco Programmable Logic Controller by Siemens Soft Errors result in faulty configuration and status information Soft Errors result in malfunction due to corrupted configuration information 1 A memory device used to load system configuration registers at boot-up time 2 Data errors caused by background radiation Modern Systems Need Reliable SRAMs 3a Soft Errors result in malfunction due to corrupted configuration information

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F Cypress Is The SRAM Market Leader Cypress is the world’s largest and most experienced Asynchronous SRAM supplier >40% market share Designed 10 generations of Asynchronous SRAMs Invests more in R&D than any other competitor does Cypress has the broadest Asynchronous SRAM portfolio 600 Asynchronous SRAMs Fast Asynchronous SRAMs from 64Kb to 32Mb MoBL ® (micropower) SRAMs with densities from 64Kb to 64Mb Industrial, automotive and rad-hard products Our newest SRAMs with on-chip ECC for single-bit error detection and correction Cypress is the most dependable Asynchronous SRAM supplier Lead times of ≤5 weeks, better than 99.4% on-time delivery Multiple qualified fabs, assembly sites and test sites Legacy part support up to 20 years Cypress is the world’s Asynchronous SRAM leader 3b

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F Asynchronous SRAM An SRAM device in which read or write operations do not require an external clock Fast SRAM High-speed Asynchronous SRAMs with access times ≤20 ns MoBL ® SRAM Low-power Asynchronous SRAMs with less than or equal to 2-µA/Mb standby current Soft Error A data error caused by background radiation Soft Error Rate (SER) The rate at which a device is predicted to encounter Soft Errors Failure-in-Time (FIT) A reliability measurement of the projected failure rate of a device One FIT equals one projected failure per billion hours Error-Correcting Code (ECC) Encoding and decoding of a bit stream using extra bits to detect and correct bit errors PowerSnooze™ SRAM Fast SRAM with an additional power-saving mode with less than or equal to 2.5-µA/Mb deep-sleep current ERR Pin An optional status pin on a Cypress Asynchronous SRAM with ECC that indicates occurrence of single bit errors Terms You Will Hear Today 4

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F FIT rates of <10 FIT/Mb are unavailable in standard SRAMs without error-correction schemes Today's standard SRAMs have FIT rates in the range of 150-1,500 FIT/Mb Mitigating Soft Errors with system-level ECC solutions forces undesirable trade-offs System-level Soft Error detection and correction solutions increase design complexity and design cycle time These solutions require additional memory and error-correction chips, increasing board space and cost High-speed, power-sensitive designs require memories with fast access time and low standby current A typical 16Mb high-speed SRAM with a 10-ns access time consumes greater than 20-mA standby current A typical 16Mb low-power SRAM with a 16-µA standby current has an access time greater than 35 ns Cypress 16Mb Asynchronous SRAM with ECC solves these problems: Assures a FIT rate of <0.1 FIT/Mb Offers a single-chip solution with on-chip ECC, reducing board space, cost and design complexity Achieves a 10-ns access time and 12-µA deep-sleep current (PowerSnooze SRAM) Cypress 16Mb Asynchronous SRAMs with ECC provide single-chip, reliable memory solutions for both high-speed, low-power applications Design Problems Engineers Face 5

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F Fast SRAM Features Low-Power SRAM Features On-Chip ECC YesNo- Soft Error Rate <0.1 FIT/Mb>150 FIT/Mb- Voltage Range V V- Access Time (Max.) 10 ns8 ns- Operating Current 110 mA115 mA- Data Retention Voltage (Min.) 1.0 V1.2 V- Deep-Sleep Mode (PowerSnooze) YesNo- On-Chip ECC YesNoYesNo Soft Error Rate <0.1 FIT/Mb>150 FIT/Mb<1 FIT/Mb<6.25 FIT/Mb Voltage Range V V V Access Time (Max.) 45 ns 55 ns Standby Current (Max.) 16 µA50 µA8 µA 40  A Data Retention Voltage (Min.) 1.0 V1.5 V 2.0 V CY7C1061xxIS61/4WVxx CY6216xxIS62/65WVxxR1LV1616Hx / R1LV1616Rx 1 No Offerings Available Cypress 16Mb Asynchronous SRAM vs. Competition’s 1 R1LV1616Rx is the latest Advanced LPSRAM offering from Renesas 7

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F Fast SRAMLow-Power SRAM (MoBL ® : More Battery Life)PowerSnooze ™ 4 Serial SRAM Non-ECCECC 3 Non-ECCECC 3 Quad-SPI, ECC 3 Asynchronous SRAM Portfolio High Density | Wide Voltage Range | Automotive A, E 1,2 | On-chip ECC 3 CY7C106x 16Mb; V 10 ns; x8, x16, x32 Ind 5, Auto E 2 ProductionSamplingDevelopment/Concept 32Mb-128Mb 2Mb-16Mb 64Kb-1Mb CY6216x 16Mb; V 45 ns; x8, x16, x32 Ind 5, Auto E 2 CY7S106x 16Mb; V 10 ns; x8, x16, x32 Ind 5, Auto E 2 CY7C185 64Kb; 5.0 V 15 ns; x8 Ind 5 CY7C Kb; 2.6, 3.3, 5.0V 10 ns; x16 Ind 5, Auto E 2 CY7C1010/11 2Mb; 3.3 V 10 ns; x8, x16 Ind 5, Auto A, E 1,2 CY7C104x 4Mb; 3.3, 5.0 V 10 ns; x4, x8, x16 Ind 5, Auto A, E 1,2, RH 6 CY7C Mb; 3.3 V 10 ns; x24 Ind 5 CY7C105x 8Mb; 3.3 V 10 ns; x8, x16 Ind 5 CY7C106x 16Mb; 1.8, 3.3 V 10 ns; x8, x16, x32 Ind 5 CY7C107x 32Mb; 3.3 V 12 ns; x8, x16 Ind 5 CY7C19x/ Kb; 3.3, 5.0 V 10 ns; x4, x8 Ind 5, Auto A 1 CY7C1019/21/100x 1Mb; 2.6, 3.3, 5.0 V 10 ns; x4, x8, x16 Ind 5, Auto A, E 1,2 CY7C1024 3Mb; 3.3 V 10 ns; x24 Ind 5 CY7C1034 6Mb; 3.3 V 10 ns; x24 Ind 5 CY Kb; 5.0 V 55 ns, 70 ns; x8 Ind 5 CY6212x 1Mb; V 45 ns; x8, x16 Ind 5, Auto A, E 1,2 CY6213x 2Mb; 1.8, V 45 ns; x8, x16 Ind 5, Auto A, E 1,2 CY6214x 4Mb; 1.8, 3.0, 2.5-5V 45 ns; x8, x16 Ind 5, Auto A, E 1,2 CY6215x 8Mb; 1.8, 3.0, 2.5-5V 45 ns; x8, x16 Ind 5, Auto A, E 1,2 CY6216x 16Mb;1.8, 3.0, 5.0 V 45 ns; x8, x16 Ind 5, Auto A 1 CY6217x 32Mb; 2.5, 3.0, 5.0 V 55 ns; x8, x16 Ind 5 CY Kb; 1.8, 3.0, 5.0V 55 ns; x8 Ind 5, Auto A, E 1,2 CY6218x 64Mb; 2.5, 3.0 V 55 ns; x8, x16 Ind 5 1 AEC-Q100 −40ºC to +85ºC 2 AEC-Q100 −40ºC to +125ºC 3 Error-correcting code 4 Fast SRAM with low-power sleep mode 5 Industrial grade −40ºC to +85ºC 6 Radiation hardened, military grade −55ºC to +125ºC Other Densities NDA Required Contact Sales Other Densities NDA Required Contact Sales Other Densities NDA Required Contact Sales Other Densities NDA Required Contact Sales 10

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F Fast SRAM Family with ECC Switches and routers IP phones Test equipment Automotive Computation servers Military and aerospace systems Applications Access time: 10 ns for 16Mb (see Family Table) Bus-width configurations: x8, x16 and x32 Wide operating voltage range: V Industrial and automotive temperature grades Industry-standard, RoHS-compliant packages Error-Correcting Code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Error indication (ERR) pin to indicate single-bit errors Features Preliminary Datasheet:Contact SalesContact Sales Collateral Family Table Sampling: Now (16Mb) Production:Q (16Mb) Availability Block Diagram 1 Byte high enable 2 Byte low enable DensityMPNAccess Time Supply Current (Max. at 85ºC) 4Mb CY7C104x10ns45mA 8Mb CY7C105x10ns60mA 16Mb CY7C106x10ns110mA 32Mb CY7C107x12ns150mA 64Mb CY7C108x12ns150mA 128Mb CY7C109x12ns200mA 11a Fast SRAM with ECC CE OEWEBHE 1 BLE 2 Address I/O Mux Address Decoder Sense Amps ECC Decoder Input Buffer ECC Encoder Control Logic SRAM Array ERR Data 8, 16, 32

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F MoBL ® SRAM Family With ECC Programmable logic controllers Handheld devices Multifunction printers Automotive Implantable medical devices Computation servers Applications Access time: 45 ns Standby current: 16 µA for 16Mb Bus-width configurations: x8, x16 and x32 Wide operating voltage range: V Industrial and automotive temperature grades Industry-standard, RoHS-compliant packages Error-Correcting Code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Error indication (ERR) pin to indicate single-bit errors Features Preliminary Datasheet: Contact SalesContact Sales Collateral Family Table Sampling: Now (16Mb) Production:Q (16Mb) Availability Block Diagram 1 Byte high enable 2 Byte low enable DensityMPN Standby Current (Max. at 85ºC) Standby Current (Typ. at 25ºC) 4Mb CY6214x7µA2.5µA 8Mb CY6215x9µA3.0µA 16Mb CY6216x16µA4.7µA 32Mb CY6217x58µA9.0µA 64Mb CY6218x58µA9.0µA 128Mb CY6219x116µA18.0µA 11b MoBL ® 3 SRAM with ECC CE OEWEBHE 1 BLE 2 I/O Mux Address Decoder Sense Amps ECC Decoder Input Buffer ECC Encoder Control Logic SRAM Array Address Data 8, 16, 32 ERR 3 More Battery Life

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F Fast SRAM Family with PowerSnooze™ Programmable logic controllers Handheld devices Multifunction printers Automotive Computation servers Applications Access time: 10 ns for 16Mb (see Family Table) PowerSnooze: Additional power-saving (deep-sleep) mode Deep-sleep current: 22 µA for 16Mb (see Family Table) Bus-width configurations: x8, x16 and x32 Wide operating voltage range: V Industrial and automotive temperature grades Industry-standard, RoHS-compliant packages Error-Correcting Code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Features Preliminary Datasheet: Contact SalesContact Sales Collateral Family Table Sampling: Now (16Mb) Production:Q (16Mb) Availability Block Diagram 2 Byte high enable 3 Byte low enable 1 Deep-sleep DensityMPNAccess Time Deep Sleep Current (Max. at 85ºC) 4Mb CY7S104x10ns10µA 8Mb CY7S105x10ns15µA 16Mb CY7S106x10ns22µA 32Mb CY7S107x12ns92µA 64Mb CY7S108x12ns92µA 128Mb CY7S109x 12ns 184µA 20 Fast SRAM with PowerSnooze TM CE OEWEBHE 2 BLE 3 Address DS 1 I/O Mux Address Decoder Sense Amps ECC Decoder Input Buffer Control Logic SRAM Array Power Management Block (Enables PowerSnooze) ECC Encoder Data 8, 16, 32 ERR 11c

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F 1.Visit the 16Mb Asynchronous SRAM with ECC webpage: 2.Download the Roadmap for Asynchronous SRAMs: 3.Request a preliminary datasheet: Contact SalesContact Sales Here’s How to Get Started 12

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F APPENDIX 15

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F 16Mb MoBL SRAM Product Selector Guide Part NumberBus WidthAccess Time# CE PinsERR PinVoltageTempPackage CY62167G30-45BVXIx1645 ns2No V-40-85°C48-VFBGA CY62167G30-45ZXIx1645 ns2No V-40-85°C48-TSOP I CY62167G-45ZXIx1645 ns2No V-40-85°C48-TSOP I CY62167GE30-45BVXIx1645 ns1Yes V-40-85°C48-VFBGA CY62167GE30-45ZXIx1645 ns2Yes V-40-85°C48-TSOP I CY62167GE-45ZXIx1645 ns2Yes V-40-85°C48-TSOP I CY62167G18-55BVXIx1655 ns2No V-40-85°C48-VFBGA CY62167GE18-55BVXIx1655 ns2Yes V-40-85°C48-VFBGA CY62168GE30-45BVXIx845 ns2Yes V-40-85°C48-VFBGA CY62168G30-45BVXIx845 ns2No V-40-85°C48-VFBGA CY62162G18-45BGXIx3245 ns2No V-40-85°C119-PBGA CY62162G30-45BGXIx3245 ns2No V-40-85°C119-PBGA 16Mb MoBL SRAM Part Numbering Decoder CY 6216 X GX XX - XX XX X XI Pb-free Industrial Temperature Grade Chip Enable: Blank = Dual Chip Enable, 1 = Single Chip Enable Package Type: BV = 48-VFBGA, Z = 48-TSOP I, BG = 119-PBGA Speed Grade: 45 = 45 ns, 55 = 55 ns Voltage Range: 30 = V, 18 = V, Blank = V Process Technology: G = 65nm; X: E = ERR pin, Blank = No ERR pin Bus Width: 7 = x16, 8 = x8, 2 = x : 16Mb MoBL SRAM Family Company ID: CY = Cypress 16a

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F 16Mb Fast SRAM Product Selector Guide Part NumberBus WidthAccess Time# CE PinsERR PinVoltageTempPackage CY7C1069G30-10ZSXIx810 ns2No V-40-85°C54-TSOP II CY7C1069GE30-10ZSXIx810 ns2Yes V-40-85°C54-TSOP II CY7C1061G30-10ZXIx1610 ns1No V-40-85°C48-TSOP I CY7C1061GE30-10ZXIx1610 ns1Yes V-40-85°C48-TSOP I CY7C1061G30-10ZSXIx1610 ns2No V-40-85°C54-TSOP II CY7C1061GE30-10ZSXIx1610 ns2Yes V-40-85°C54-TSOP II CY7C1061G30-10BVXIx1610 ns2No V-40-85°C48-VFBGA CY7C1061GE30-10BVXIx1610 ns2Yes V-40-85°C48-VFBGA CY7C1061G30-10BV1XIx1610 ns1No V-40-85°C48-VFBGA CY7C1061G30-10BVJXIx1610 ns2No V-40-85°C48-VFBGA CY7C1061G18-15BV1XIx1615 ns1No V-40-85°C48-VFBGA CY7C1062G30-10BGXIx3210 ns3No V-40-85°C119-PBGA CY7C1062GE30-10BGXIx3210 ns3Yes V-40-85°C119-PBGA CY 7C106 X GX XX - XX XXX XI Pb-free Industrial Temperature Grade Package Type: Z = 48-TSOP I, ZS = 54-TSOP II, BVX = 48-VFBGA, BG = 119-PBGA Speed: 10 = 10 ns, 15 = 15 ns Voltage Range: 18 = V, 30 = V, Blank= V Process Technology: G = 65nm; X: E = ERR pin, Blank = No ERR pin Bus Width: 1 = x16, 2 = x32, 9 = x8 7C106: 16Mb Fast SRAM Family Company ID: CY = Cypress 16Mb Fast SRAM Part Numbering Decoder 16b

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F 16Mb PowerSnooze SRAM Product Selector Guide Part NumberBus WidthAccess Time# CE PinsERR PinVoltageTempPackage CY7S1061G30-10BVXIx16 10 ns1No V-40-85°C 48-VFBGA CY7S1061G30-10ZXIx16 10 ns1No V-40-85°C48-TSOP I CY7S1061G30-10ZSXIx16 10 ns2No V-40-85°C 54-TSOP II CY7S1061GE30-10ZXIx16 10 ns1Yes V-40-85°C48-TSOP I CY7S1062G-10BGXIx32 10 ns3No V-40-85°C 119-PBGA CY7S1062G-15BGXIx32 15 ns3No V-40-85°C 119-PBGA CY 7S106 X GX XX - XX XXX I Temperature Grade: Industrial Pb-free Package Type: ZX = 48-pin TSOP I, ZSX = 54-pin TSOP II, BVX = 48-ball VFBGA Speed: 10 = 10 ns, 15 = 15 ns Voltage Range: 18 = V, 30 = V Process Technology: G = 65nm; X: E = ERR pin, Blank = No ERR pin Bus Width: 1 = x16, 2 = x32 7S106: 16Mb PowerSnooze Family (deep-sleep feature) Company ID: CY = Cypress 16Mb PowerSnooze SRAM Part Numbering Decoder 16c

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F References and Links Asynchronous SRAM Roadmap: Cypress Product Selector Guide: Knowledge Base Articles: Asynchronous SRAM Datasheets: Application Notes: Getting Started with Asynchronous SRAM: SRAM Board Design Guidelines: Asynchronous SRAM Webpage: 18

Owner: SAYD16Mb Asynchronous SRAM with ECC New Product Introduction (Engineering) Rev *F 16Mb SRAM With ECC Solution Value Competitor Asynchronous Fast SRAM without ECC Price: $ BOM Integration Additional SRAM for ECC data 2 Price: $ Additional Value Cost of Programming MCU for ECC logic Value Added: $ Board Space Savings Value Added: $ $15.34 $3.23 $0.15 $0.01 $0.16 $18.73 Competitor Additional SRAM for ECC data BOM Integration Value Cost of Programming MCU for ECC logic Board Space Savings Total Additional Value Total Value Delivered Async Fast SRAM with ECC: Total Cost: 11% Total Savings: CY7C1061G30-10BVJXI $16.67 $ Digikey 1ku price for IS61WV102416BLL-10MLI (16Mb SRAM) 2 4Mb additional SRAM is used to implement ECC scheme (to store additional 6 parity bits per 32 bits of data) 3 Digikey 1ku price for IS61WV25616BLL-10TL (4Mb SRAM) 4 5 man-weeks at $3,000 per man-week = $15,000 (amortized over 100ku) square-inch space saving at $0.05 per square inch = $