©2000 Addison Wesley Little- and big-endian memory organizations.

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Presentation transcript:

©2000 Addison Wesley Little- and big-endian memory organizations

©2000 Addison Wesley ARM operating modes and register usage.

©2000 Addison Wesley Exception vector addresses

©2000 Addison Wesley The ARM condition code field

©2000 Addison Wesley ARM condition codes

©2000 Addison Wesley Branch and Branch with Link binary encoding

©2000 Addison Wesley Branch (with optional link) and exchange instruction binary encoding condRm L H 24-bit signed word offset (1) BX|BLX Rm (2) BLX label

©2000 Addison Wesley Software interrupt binary encoding

©2000 Addison Wesley Data processing instruction binary encoding cond0 operand 2 #opcodeSRnRd destination register first operand register set condition codes arithmetic/logic function 8-bit immediate #rot Rm #shift Rm Rs Sh 0 10 immediate alignment immediate shift length shift type second operand register register shift length

©2000 Addison Wesley ARM data processing instructions

©2000 Addison Wesley Multiply instruction binary encoding

©2000 Addison Wesley Multiply instructions

©2000 Addison Wesley Count leading zeros instruction binary encoding

©2000 Addison Wesley Single word and unsigned byte data transfer instruction binary encoding

©2000 Addison Wesley Half-word and signed byte data transfer instruction binary encoding

©2000 Addison Wesley Data type encoding

©2000 Addison Wesley Multiple register data transfer instruction binary encoding

©2000 Addison Wesley Swap memory and register instruction binary encoding

©2000 Addison Wesley Status register to general register transfer instruction binary encoding

©2000 Addison Wesley Transfer to status register instruction binary encoding cond0 operand #field field mask 8-bit immediate Rm operand register 1 0R SPSR/CPSR #rot immediate alignment

©2000 Addison Wesley Coprocessor data processing instruction binary encoding

©2000 Addison Wesley Coprocessor data transfer instruction binary encoding

©2000 Addison Wesley Coprocessor register transfer instruction binary encoding

©2000 Addison Wesley Breakpoint instruction binary encoding

©2000 Addison Wesley Arithmetic instruction extension space

©2000 Addison Wesley Control instruction extension space

©2000 Addison Wesley Data transfer instruction extension space

©2000 Addison Wesley Coprocessor instruction extension space

©2000 Addison Wesley Undefined instruction space

©2000 Addison Wesley Summary of ARM architectures Core Architecture ARM1 v1 ARM2 v2 ARM2as, ARM3 v2a ARM6, ARM600, ARM610 v3 ARM7, ARM700, ARM710 v3 ARM7TDMI, ARM710T, ARM720T, ARM740T v4T StrongARM, ARM8, ARM810 v4 ARM9TDMI, ARM920T, ARM940T v4T ARM9ES v5TE ARM10TDMI, ARM1020E v5TE