Tightly coupled INS/GPS system using particle filter D0928- system architecture and math functions Part B - Final presentation Students: Royzman Danny Peleg Nati Supervisor: Fiksman Evgeni

Agenda Controllers Background ▫Main controllers ▫Local controllers Infrastructure – Controllers ▫Review ▫General results display ▫G.P.S Phase 2 ÷ Phase 5 R&D Difficulties

Controllers Background controllers – modus operandi: The system has two modes of operation. I.N.S mode G.P.S mode In order to achieve the system goals in efficient way, the operation modes were divided into ten different phases. One I.N.S Phase Nine G.P.S Phases

Controllers Background Main controllers - modus operandi : The system implements 4 main controllers. Main controller1 passes commands to Main controller2. Main controller2 passes commands to Main controller3 and so on. Every Main controller returns acknowledge. Every Main controller passes commands to his local controller.

Controllers Background Main controllers – Main controller1: Main controller1 is the main controller of the system. Main controller1 triggers (by counting) the required system mode by implementing a sequencer block. sequencer

Controllers Background Main controllers - modus operandi : The data and commands are send through master\slave transceivers.

Controllers Background Local controllers – modus operandi: The system implements 4 local controllers.

Controllers Background Local controllers - modus operandi : Each Local controller controls the relevant logic.

Infrastructure - Controllers Events – general revision

Infrastructure - Controllers Events – timing chart revision

Infrastructure - Controllers I.N.S Phase – revision

Infrastructure - Controllers G.P.S Phase1 – revision

Infrastructure - Controllers Results display Full system operation presented in the GUI developed for the project. Thanks to the insight advised by the lab staff during part1 presentation, the results are displayed in signal tap.

Infrastructure - Controllers G.P.S Phase2 – block scheme

Infrastructure - Controllers G.P.S Phase2 – IC1

Infrastructure - Controllers G.P.S Phase2 – Local controller1 State Machine Diagram

Infrastructure - Controllers G.P.S Phase2 – IC1 Signal Tap

Infrastructure - Controllers G.P.S Phase2 – IC2

Infrastructure - Controllers G.P.S Phase2 – Local controller2 State Machine Diagram

Infrastructure - Controllers G.P.S Phase2 – Local controller2 Signal Tap

Infrastructure - Controllers G.P.S Phase3 – block scheme

Infrastructure - Controllers G.P.S Phase3 – Data flow In order to demonstrate data flow hardware alternation is needed: 1.Data supplier inside GPS Neff block 2.C.L in frame2

Infrastructure - Controllers G.P.S Phase3 – Data supplier inside GPS Neff block

Infrastructure - Controllers G.P.S Phase3 – Combinational Logic in frame2

Infrastructure - Controllers G.P.S Phase3 – IC1

Infrastructure - Controllers G.P.S Phase3 – Local controller1 State Machine Diagram

Infrastructure - Controllers G.P.S Phase3 – IC1 Signal Tap

Infrastructure - Controllers G.P.S Phase3 – IC2

Infrastructure - Controllers G.P.S Phase3 – Local controller2 State Machine Diagram

Infrastructure - Controllers G.P.S Phase3 – IC2 Signal Tap

Infrastructure - Controllers G.P.S Phase3 – IC3

Infrastructure - Controllers G.P.S Phase3 – Local controller3 State Machine Diagram

Infrastructure - Controllers G.P.S Phase3 – IC3 Signal Tap

Infrastructure - Controllers G.P.S Phase4 – block scheme

Infrastructure - Controllers G.P.S Phase4 – Data flow In order to demonstrate data flow hardware alternation is needed: Data supplier in frame1

Infrastructure - Controllers G.P.S Phase3 – Data supplier in frame1

Infrastructure - Controllers G.P.S Phase4 – IC1

Infrastructure - Controllers G.P.S Phase4 – Local controller1 State Machine Diagram

Infrastructure - Controllers G.P.S Phase4 – IC1 Signal Tap

Infrastructure - Controllers G.P.S Phase4 – IC2

Infrastructure - Controllers G.P.S Phase4 – Local controller2 State Machine Diagram

Infrastructure - Controllers G.P.S Phase4 – IC2 Signal Tap

Infrastructure - Controllers G.P.S Phase4 – IC3

Infrastructure - Controllers G.P.S Phase4 – Local controller3 State Machine Diagram

Infrastructure - Controllers G.P.S Phase4 – IC3 Signal Tap

Infrastructure - Controllers G.P.S Phase5 – block scheme

Infrastructure - Controllers G.P.S Phase5 – IC1

Infrastructure - Controllers G.P.S Phase5 – Local controller1 State Machine Diagram

Infrastructure - Controllers G.P.S Phase5 – IC1 Signal Tap

Infrastructure - Controllers G.P.S Phase5 – IC2

Infrastructure - Controllers G.P.S Phase5 – Local controller2 State Machine Diagram

Infrastructure - Controllers G.P.S Phase5 – IC2 Signal Tap

Infrastructure - Controllers G.P.S Phase5 – IC3

Infrastructure - Controllers G.P.S Phase5 – Local controller3 State Machine Diagram

Infrastructure - Controllers G.P.S Phase5 – IC3 Signal Tap

Infrastructure - Controllers G.P.S Phase5 – IC4

Infrastructure - Controllers G.P.S Phase5 – Local controller4 State Machine Diagram

Infrastructure - Controllers G.P.S Phase5 – IC4 Signal Tap

R&D Difficulties Long compilation time – we reduced the compilation needed by using signal tap. Great system complexity results in long R&D period.

Q&A

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