Current Status of RICH LVL-1 Trigger Module Takashi Matsumoto and Ken Oyama Presentation Outline Topics Geometry of Trigger Tile Required function of RICH LVL-1 Block diagram of LVL-1 Module Another scheme (with MuID ROC) Development of prototype Ver.2 Comparison of two LVL-1 schemes Conclusion

Topics Old version of RICH trigger module is obsolete. 32 G-Links to Local LVL-1 Two different new layouts of RICH trigger are presented. 1. Followed by MuID ROC 2. Digital Processing in RICH LVL-1 trigger module. Similar to old style, but # of G-Links is less than 16, and data format can be is same as output of ROC.

Geometry of Trigger Tile 80 PMTs 5PMTs 4 PMTs Trigger Tile 16 trigger tiles are processed on a “SAME” LVL-1 Module. RICH PMT array of a side (1/4 of entire PHENIX) has 1,280 PMTs (64 non overlapped trigger tiles) ……. ….. Preamps = 16 tiles

Make 4x5 PMT current sum from 5 AMU/ADC Modules Make 4x5 PMT current sum from 5 AMU/ADC Modules Current Sum of 4x5 PMTs Current Sum of 4 PMTs i1i2i3i4 i5 I total = i1+i2+i3+i4+i5 RICH Chip AMU/ADC Modules Back Plane RICH chips on AMU/ADC module make 4 PMTs current sum. Output of 5 RICH chips are summed up on the Back-Plane again.

Required function of RICH LVL-1 (old scheme) Required function for RICH LVL1 module (only 3 things) -Current to Voltage conversion -AD Conversion -Send data to Local LVL-1 via G-LINK Configuration Input - 16 channels/module - 4x5 PMTs current sum per channel - Dynamic Range 2.5mA(offset) to 7 mA (corresponds 0 to 70 photon) Output - 2 G-LINK/module (total = 32) Latency < 200ns

Block Diagram of LVL-1 Trigger Module (old scheme) Upper half of LVL-1 module and only one channel are shown. 4x5 PMTs Current Sum Reference Vcc CLK Serial LVL1 Controller Control line for upper Control line for lower 3 State Buffer Trailer 4 bits ADC CLK 10bit ADC bits To G-LINK 20 bits 3State timing Signal line Control line Data Structure data1 data2 data3 data4 data5

A New Scheme (with MuID ROC) x16 MuID ROC Threshold OR’s New LVL-1 A RICH LVL-1 Trigger Module Trigger Sum Reference 16 analog signal output/module 16 x 4 analog signal are fed from other module Send analog sum signals from RICH LVL-1 module to MuID ROC MuID ROC is already developed. Some threshold cut are required on the RICH LVL-1 module? If so, it is not so easy to design new analog circuit.

Development of Prototype Ver.2 (Digital Processing) # of ADCs are same as old scheme. Output of ADCs are followed by a logic processing (threshold, OR’s, etc.) unit. Programmable. (Use Altera CPLD – around $100/chip) We have much experience to design digital circuit. +5V bits ADC CPLD (FLEX10K20) Threshold OR’s cupper outputs or G-LINKs with same format as MuID ROC? ADC outputs from other 15 channels Another new scheme RICH group propose.

With MuID ROC Digital processing on RICH LVL-1 module Threshold setup & logic OR’s are performed in MuID ROC. RICH LVL-1 module has to output 256 (coaxial ? Its question) cables of analog sum which results many cables and worry of analog noise due to GND loop. MuID ROC is already developed. Analog signals are converted to digital data IN a RICH crate  No worry of additional noise due to cabling. Threshold setup and OR’s are performed at RICH LVL-1 module (also re-configurable). RICH LVL-1 module outputs digitized data that needs less cable. 16 flat cables (or G-Links) { can be reduced to 8 cables (or G-Links) ?} Prototype will come soon. No further operation procedures. Comparison of two LVL-1 schemes