1 Presented by: Paul Mesa Vikram Rao Electrical Engineering Dept. UCLA Inverse Inductance and VPEC Modeling

2 References A. Devgan, et. al. “ How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element, K ” in ICCAD, H. Yu, L. He, “ A Provable Passive and Cost-Efficient Model for Inductive Interconnects ”, IEEE Transactions in CAD, 2005.

3 Outline n Inductance Review n Inverse L l Partial Inductance Issues l Inverse L Matrix l Results n VPEC (Vector Potential Equivalent Circuit)

4 Partial Inductance Issues n Large, densely coupled network representation l Makes simulation time large l Only practical for small examples n Difficult to reduce matrix l Distant mutual inductances cannot be discarded, meaning no shielding effect. l L matrix is not diagonally dominant u Removing “unimportant” terms to simplify the problem can result in an unstable circuit model (loses passivity)

5 K Matrix (L -1 ) n Propose a new circuit element, K l K = Inverse of Partial Inductance Matrix L n Origin l Inductance for transmission line structures u [L loop ] = μ 0 ε 0 [C 0 ] -1 è Capacitance matrix has locality, sparsity and diagonal dominance è Maybe L -1 has similar properties as C?

6 Advantages of K n Locality and Sparsity similar to Capacitance Matrix l Can construct libraries or analytical formulas for K, similar to what was done for C, to make predicting inductance for the full chip more practical n Diagonally Dominant l Truncation of off-diagonal elements guarantees stability of subsequent RKC equivalent circuit n RKC Simulation l Directly extracting and simulating K makes full chip extraction more feasible than using partial inductance matrices

7 Locality - 5 Parallel Bus Example n Length=20um Cross section=2x2um Spacing=5um n Partial Inductance matrix calculated by FastHenry n Locality: n L 15 = 12.1% of L 11 n K 15 = 3.7% of K 11

8 Locality - 5 Parallel Bus Example (cont’d) n Truncating K matrix by removing K 15 and K 51, we get K’ n Inverting K’ we get L’ n We calculate L loop15 =L 11 +L 55 +L 15 +L 51 n Calculating L loop15 ’ using L’, we see a difference of 4% of L loop15 n If we remove L 15 and L 51 from L to get a truncated L matrix, L’’, we get L loop15 ’’ as a difference of 14% of L loop15

9 K-based Method n K- based method l Calculate partial inductance matrix L small,i structure enclosed in a small window, i l Calculate K small,i matrix by inverting corresponding L small,I matrix l Compose K big matrix using columns from K small,I matrix corresponding to the aggressor (similar techniques used in capacitance extraction) l Simulate RKC circuit u How are R and C calculated? PEEC

10 Localized Extraction with K

11 An Example

12 K-method Properties n Pros l Locality and Sparsity similar to Capacitance Matrix l Diagonally dominant, allows truncation of off-diagonal elements and preserves passivity l RKC Simulation extracting and simulating K makes full chip extraction more feasible than using partial inductance matrices n Cons l Cannot be simulated in SPICE u Needs special tool to simulate RKC circuit

13 PEEC Model

14 PEEC Model

15 n Distributed RLCM circuit has coupling inductance between any two segments l Total 3,278,080 elements for 128b bus with 20 segments per line, needs 162M storage of SPICE netlist n De-facto Partial Element Equivalent Circuit (PEEC) model is expensive l Massively coupled partial inductance l Order of circuit matrix is huge Partial Element Equivalent Circuit (PEEC) Disadvantages of L matrix

16 Inductance Matrix Sparsification n Inverse of inductance matrix l K-element [Devegan:ICCAD’00] u Observe the inverse of inductance matrix is strictly diagonal dominant such that enable passively truncating small off-diagonal elements u Need modify SPICE to handle K-element n Vector Potential Equivalent Circuit (VPEC) l Integration based [Paceli:ICCAD’02] u A physically developed model to describe inductance by effective resistance u Locality assumption is inaccurate, and no efficient method to obtain the value of effective resistance l Inversion based [Yu and He: DAC’03] u A rigorous derivation of VPEC model u An efficient calculation method is proposed u Need full inversion that is expensive

17 Vector Potential Equivalent Circuit  Prove that circuit matrix in VPEC model is strictly diagonal dominant and hence passive  Enable various passivity preserved sparsifications  Derive inversion based VPEC model from first principles  Replace inductances with effective resistances  Develop closed-form formula for effective resistances  Enable direct and faster simulation in SPICE Our Contribution

18 Vector Potential Formulation  Vector potential for filament i ith Filament

19 Integral Equation for Inductive Effect Volume Integration Line Integration (1) (2)

20 VPEC model for any two filaments VPEC Circuit Model n Effective Resistances n Vector Potential Current Sources n Vector Potential Voltage Sources n Unit Self-Inductance n Much fewer reactive elements (inductances) l Leads to faster SPICE simulation

21 VPEC Circuit Model n It consists of electronic circuit and magnetic circuit l Electronic circuit inherits resistances and capacitances from PEEC l Magnetic circuit uses effective resistance to model inductances l Controlled current/voltage sources are used to connect the two circuits l Unit self-inductance is used to take the time-derivative and also store the magnetic energy

22 Inversion Based VPEC Model

23 Closed-form Extraction of Effective Resistance  Major computing effort is inversion of inductance matrix  LU/Cholesky factorization  GMRES/GCR iteration  System equation based on G-element  System equation based on K-element i.e.

24 Property of VPEC Circuit Matrix Main Theorem The circuit matrix is strictly diagonal- dominant and positive-definite Corollary The VPEC model is still passive after truncation

25 VPEC Model Simulation Flow Extract PEEC elements via either formula or FastHenry/FastCap If (system size is small) Invert L matrix via LU or iterative method generate full VPEC circuit Sparsify full VPEC by numerical or geometrical truncation Else Specify coupling window size Heuristic windowing extraction and VPEC generation Directly simulate in SPICE

26 Accuracy Check Full PEEC vs. full VPEC vs. localized VPEC  Full VPEC is as accurate as Full PEEC  Localized VPEC model is not accurate

27 Non-regular Conductor Non-bus Structure: Three-turn single layer on-chip spiral inductor  Full VPEC model is accurate and can be applied for general layout

28 Numerical Sparsification Example: truncation of 5-bit bus with threshold 0.09  Drop off-diagonal elements with ratio below the threshold  Larger effective resistors are less sensitive to current change  Calculate the ratio between off-diagonal elements and the diagonal element of every row Given the full matrix

29 Truncation Threshold  Supply voltage is 1V  VPEC runtime includes the LU inversion  Full VPEC model is as accurate as full PEEC model but yet faster  Increased truncation ratio leads to reduced runtime and accuracy Models and Settings (threshold) No. of Elements Run-time (s)Average Volt. Diff. (V) Standard Dev. (V) Full PEEC V Full VPEC e-6V3.41e-4V Truncated VPEC (5e-5) e-6V4.97e-4V Truncated VPEC (1e-4) e-5V1.37e-3V Truncated VPEC (5e-4) e-4V5.20e-3V 128-bit bus with one segment per line

30 Geometry Based Sparsification  Windowed VPEC  neighbor-window (nix, niy ) for aligned coupling and forwarded coupling  consider only forward coupling of same wire For the geometry of aligned bus line

31 Geometrical Sparsification Results 32-bit bus with 8 segment per line  Decreased window size leads to reduced runtime and accuracy  Windowed VPEC has high accuracy for window size as small as (16,2) Models and Settings No. of Elements Run Time (s)Avg. Volt. Diff. (V) Standard Dev. (V) Full PEEC Full VPEC (32, 8) e-56.26e-4 Windowed (32, 2) e-51.84e-3 Windowed (16, 2) e-44.56e-3 Windowed (8, 2) e-48.91e-3 Normalized e-42.96e-3

32 Full Inversion? inverttruncate L L G  Need more efficient yet accurate sparsification  Truncating based sparsifcation unitizes within two steps  Full inversion - > Truncating  May be memory intensive for large size system  May be not accurate by simple direct truncation  Construct the VPEC model through different sub-matrices

33 Windowing Technique L G

34 Windowing Sparsification Results Input: apply 1V transient at 1 st bit of 128-bit bus Output: observe at far end of 64 th bit bus HW: heuristic windowing; TW: truncation window 8.20e e TW VPEC (b=16) 4.29e e HW VPEC (b=8) 1.39e e TW VPEC (b=8) 2.99e e HW VPEC (b=16) 2.64e e TW VPEC (b=64) 1.57e e HW VPEC (b=64) 2.43e e Full VPEC Full PEEC Stand. Dev. (V) Avg. Volt. Diff. (V) Simulation Time (s) SPICE MEM (kb) No. of Elements Models and Window Size

35 Runtime Scaling  Circuit: one segment per line for buses  The runtime grows much faster for full VPEC than for full PEEC  full VPEC is 47x faster for 256-bit bus due to reduced number of reactive elements  Sparsified VPEC reduces runtime by 1000x with bounded error for large scale interconnects

36 Recap of Sparsification of VPEC Model  Derived inversion based VPEC from first principle  Inductance is replaced by effective resistances (with additional controlled sources) via a unique closed-form formula  Enable direct SPICE simulation  The full VPEC transient simulation is faster than full PEEC  Enable direct truncation based sparsfication  Circuit matrix under VPEC model is strictly diagonal dominant  Shown that full VPEC has the same accuracy as full PEEC but faster  Proved that VPEC model remains passive after truncation  The matrix size of RLCM circuit is still high  Model-order-reduction for VPEC

BACKUP SLIDES / EXCESS SLIDES

38 Maxwell’s Equations

39 VPEC model for any two filaments VPEC Circuit Model Effective Resistances (1) (2)

40 VPEC model for two filaments VPEC Circuit Model Vector Potential Current Sources

41 VPEC Circuit Model VPEC model for two filaments Vector Potential Voltage Sources