APV25, Clock and Trigger M.Friedl HEPHY Vienna. 2Markus Friedl (HEPHY Vienna)18 Mar 2009 APV25 Please refer to my December 2008 meeting slides for details.

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APV25, Clock and Trigger M.Friedl HEPHY Vienna

2Markus Friedl (HEPHY Vienna)18 Mar 2009 APV25 Please refer to my December 2008 meeting slides for details about APV25 (SVD session) In Nov/Dec 2008 beam test, we confirmed that APV works perfectly fine with both –42.4 MHz clock (=RF/12)  3.5 µs max L1 latency –31.8 MHz clock (=RF/16)  4.7 µs max L1 latency We can make the APV25 clock switchable Schematics of one channel

3Markus Friedl (HEPHY Vienna)18 Mar 2009 APV25 Pipeline & Trigger Simulation

4Markus Friedl (HEPHY Vienna)18 Mar 2009 APV25 Trigger Restrictions (1) Minimum L1 distance of 6 APV clocks – Irrelevant in case of 500ns dead time as requested by ECL (2) Maximum pipeline filling – also affected by such dead time requirement

5Markus Friedl (HEPHY Vienna)18 Mar 2009 APV Trigger Simulation Input: CLK, L1 rate Model: APV25 state machine, exponential trigger distribution Output: FIFO filling histogram, trigger loss, Poisson distribution to check randomness of simulated triggers Download: (needs Labwindows/CVI 8.1 run- time engine from

6Markus Friedl (HEPHY Vienna)18 Mar 2009 Results – No External Dead Time Requirement Min Lost: trigger restriction (1) = too little distance FIFO Lost: trigger restriction (2) = too many pending readouts Nakao-san wishes <3% dead L1=30kHz  OK (0.87%) for 42.4MHz clock, slightly higher (3.43%) at 31.8MHz

7Markus Friedl (HEPHY Vienna)18 Mar 2009 Results – External 500 ns Dead Time Requirement Nakao-san‘s wish (<3% dead L1=30kHz) met in both cases  0.42% for 42.4MHz clock and 2.7% at 31.8MHz 500ns dead time (as required by ECL) not accounted for APV25 –Hence no minimum lost figure always zero

8Markus Friedl (HEPHY Vienna)18 Mar 2009 Summary

9Markus Friedl (HEPHY Vienna)18 Mar 2009 Summary APV25 has trigger limitations due to (1) Minimum L1 distance of 6 APV clocks (2) Maximum pipeline filling APV25 can operate at both 42.4MHz (RF/12) or 31.8MHz (RF/16) clocks In case of no external limitation, we 30kHZ L1: –0.87% for 42.4MHz clock, 3.43% at 31.8MHz (see December slides for more detail) With 500ns dead time as requested by ECL we get –0.42% for 42.4MHz clock, 2.7% at 31.8MHz –Conclusion: With 500ns ECL dead time, both frequencies are fine according to Nakao-san‘s wish of <3% APV25 dead L1=30kHz