© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.

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© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust © 2008 Pearson Education Chapter 8

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed In this lecture we cover: 8-1 Asynchronous Counters 8-2 Synchronous Counters 8-3 Up/Down Synchronous Counters 8-4 Design of Synchronous Counters

 Q 1 is connected to clk, Q 2 and Q 3 are clocked by Q’ of the preceding stage (hence called asynchronous or ripple counter) A Three-Bit Up-Counter

A Three-Bit Down-Counter  Q 1 is connected to clk, Q 2 and Q 3 are clocked by Q of the preceding stage (asynchronous or ripple counter)

Clock cycle 0080 Q 2 Q 1 Q 0 Q 1 changes Q 2 Derivation of the Synchronous Up-Counter  Q 0 changes with clk, Q 2 changes when previous state of Q 0 was 1, and Q 3 changes when previous state of Q 1 and Q 0 were 1

A Four-Bit Synchronous Up-Counter

T Q Q Clock T Q Q Enable Clear T Q Q T Q Q Inclusion of Enable and Clear Capability

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Next lecture covers LCL presentation 2: Counter Shift register The next theory lecture cover: 10-1 Memory Basics 10-2 The Random Access Memory (RAM) 10-3 The Read Only Memory (ROM)