Fabrication of Poly-Si TFT on Flexible Thin Glass Substrate Yoochul Jung, Sunghwan Won, D.G. Ast (Cornell University, Dep. of Mat. Sci. Eng) 2006.06.28.

Slides:



Advertisements
Similar presentations
Display Systems and photosensors (Part 2)
Advertisements

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course Basic semiconductor physics.
Solid Propellant Micro-rockets: Application, Design and Fabrication ME 381 Final Presentation 12/12/02 Northwestern University Nik Hrabe Albert Hung Josh.
Abstract This paper proposes a novel flexible display technologies using ultra-thin glass substrate. Flexible thin glass substrate as a panel material.
Chapter 2 Modern CMOS technology
1 Microelectronics Processing Course - J. Salzman - Jan Microelectronics Processing Oxidation.
1/38 Alternative Substrates Y-C Jung,S-H Won, D.G. Ast.
School of Electrical and Electronic Engineering Queen’s University Belfast, N.Ireland Course Tutor Dr R E Hurley Northern Ireland Semiconductor Research.
Techniques of Synthesizing Wafer-scale Graphene Zhaofu ZHANG
Woodpile Structure Fabrication Chris McGuinness July 8, 2009 Workshop on Novel Concepts for Linear Accelerators and Colliders Working Group 2: Dielectric.
SEMICONDUCTOR DEVICE FABRICATION AN OVERVIEW Presented to EE 2212 Text Section 2.11 Supplement 24 September 2014.
MSE-630 Gallium Arsenide Semiconductors. MSE-630 Overview Compound Semiconductor Materials Interest in GaAs Physical Properties Processing Methods Applications.
Introduction to Flexible Electronics I Michael Thompson – MS&E Cornell University LIFE ERC Discussions February 24, 2007.
Surface micromachining
1 ME 381R Fall 2003 Micro-Nano Scale Thermal-Fluid Science and Technology Lecture 18: Introduction to MEMS Dr. Li Shi Department of Mechanical Engineering.
ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.
Organic Electronics Yousof Mortazavi VLSI Course Presentation December 2004.
Semiconductor Device and Processing Technology
Technologies for integrating high- mobility compound semiconductors on silicon for advanced CMOS VLSI Han Yu ELEC5070.
반도체 제작 공정 재료공정실험실 동아대학교 신소재공학과 손 광 석 隨處作主立處開眞
Comparison of various TSV technology
1. A clean single crystal silicon (Si) wafer which is doped n-type (ColumnV elements of the periodic table). MOS devices are typically fabricated on a,
Project Title Mechanics of thin film on wafer R 詹孫戎.
SEMINAR PRESENTATION ON IC FABRICATION PROCESS
This Materials World Network collaborative program brings researchers (Alford and Mayer) from Arizona State University (ASU) and (D. Adams and N. Tile)
1 Confidential Proprietary Application of layers with internal stress for silicon wafer shaping J. Šik 1, R. Lenhard 1, D. Lysáček 1, M. Lorenc 1, V. Maršíková.
EE235 Presentation I CNT Force Sensor Ting-Ta YEN Feb Y. Takei, K. Matsumoto, I. Shimoyama “Force Sensor Using Carbon Nanotubes Directly Synthesized.
Lecture 24a, Slide 1EECS40, Fall 2004Prof. White Lecture #24a OUTLINE Device isolation methods Electrical contacts to Si Mask layout conventions Process.
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #3. Diffusion  Introduction  Diffusion Process  Diffusion Mechanisms  Why Diffusion?  Diffusion Technology.
MonolithIC 3D Inc., Patents Pending MonolithIC 3D ICs October MonolithIC 3D Inc., Patents Pending.
Lecture 18 OUTLINE The MOS Capacitor (cont’d) – Effect of oxide charges – Poly-Si gate depletion effect – V T adjustment Reading: Pierret ; Hu.
Application of Silicon-Germanium in the Fabrication of Ultra-shallow Extension Junctions of Sub-100 nm PMOSFETs P. Ranade, H. Takeuchi, W.-H. Lee, V. Subramanian,
IC Fabrication Overview Procedure of Silicon Wafer Production
Surface Micromachining Dr. Marc Madou, Fall 2012, UCI Class 10.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.
Lecture 18 OUTLINE The MOS Capacitor (cont’d) – Effect of oxide charges – V T adjustment – Poly-Si gate depletion effect Reading: Pierret ; Hu.
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
MEMS devices: How do we make them? Sandia MEMS Gear chain Hinge Gear within a gear A mechanism.
Fowler-Nordheim Tunneling in TiO2 for room temperature operation of the Vertical Metal Insulator Semiconductor Tunneling Transistor (VMISTT) Lit Ho Chong,Kanad.
11/8/ Plasma Assisted Surface Modification: Low Temperature Bonding SFR Workshop November 8, 2000 Yonah Cho, Adam Wengrow, Chang-Han Yun Nathan Cheung.
Thin Oxides The new frontier. Volume 43, No Special Issue on Ultrathin Oxides.
MEMS 2016 Part 2 (Chapters 29 & 30)
Wafer bonding (Chapter 17) & CMP (Chapter 16)
1 Device Fabrication And Diffusion Overview 5 and 8 February 2016 Silicon Wafer Production-Refer to Chapter “0” Prologue Raw material ― Polysilicon nuggets.
Patterning - Photolithography
KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering Lecture V Thermal Processes.
MIT Amorphous Materials 11: Amorphous Silicon Macroelectronics
Wafer bonding (Chapter 17) & CMP (Chapter 16)
Lecture 18 OUTLINE The MOS Capacitor (cont’d) Effect of oxide charges
7. Surface Micromachining Fall 2013 Prof. Marc Madou MSTB 120
Simplified process flow for bonding interface characterization
Microelectronic Fabrication
Introduction Thin films of hydrogenated amorphous silicon (a-Si:H) are used widely in electronic, opto-electronic and photovoltaic devices such as thin.
Temperature Sensors on Flexible Substrates
Fabrication Steps of Detectors
CMOS Process Flow.
Nanoscale Dielectric Films by Plasma Oxidation
MIT Amorphous Materials 11: Amorphous Silicon Macroelectronics
Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si
Process flow part 2 Develop a basic-level process flow for creating a simple MEMS device State and explain the principles involved in attaining good mask.
Layer Transfer Using Plasma Processing for SMART-Wafer
Thermal oxidation Growth Rate
Device Fabrication And Diffusion Overview
BONDING The construction of any complicated mechanical device requires not only the machining of individual components but also the assembly of components.
Layer Transfer Technology for Micro-System Integration
IC Fabrication Overview Procedure of Silicon Wafer Production
Sung June Kim Chapter 18. NONIDEAL MOS Sung June Kim
Device Fabrication And Diffusion Overview
Presentation transcript:

Fabrication of Poly-Si TFT on Flexible Thin Glass Substrate Yoochul Jung, Sunghwan Won, D.G. Ast (Cornell University, Dep. of Mat. Sci. Eng)

Outline 1.Motivation 2.Comparison of Polymer and Glass substrates. 3.Processing of Pocket Fabrication 4. Characteristics of poly-Si TFT on Flexible Glass Substrate 5. Summary and Discussion Ast Group

Motivation – Development of “Displays” CRT TFT (a-Si) -LCD TFT (poly-Si) -LCD Advantages of flexible display Less apt to break, Roll-up, Less weight and volume Flexible Displays are being developed as the next generation displays Taken from Philips Inc. Ast Group

Polymer Based Display Vs. Glass Based Display Large CTE (PET, 65 x /°C) Low and adaptable CTE (Si, 2 x /°C) xx surface finish to less compatible material High surface finish α-Si:H Compatible material with Low temperature oxide α-Si:H Max. processing temperature ~ 300 °CMax. processing temperature ~ 600 °C Polymer substrates Glass substrates Ast Group Laser recrystallized Si with barrier layersCVD poly-Si MILC silicon Laser recrystallized Si (no thermal barrier) Mismatched with Si, thermal stress

LPCVD Poly-Si TFT on MS Glass * Microsheet borosilicate glass contains boron * Boron acts as p-dopant in Si * Boron may migrate into Si-electronics during poly-deposition * Barrier layer is required 1 * Mechanical support is required to handle Microsheet glass 2 For 1, SiN X, LTO layer used for barrier layer For 2, Special support needs to be designed… Ast Group Microsheet™ Glass Wafer Barrier layer (SiN x ) Poly Si Gate DrainSource Barrier layer (SiN x ) Gate SiO 2

Si-Framed Pocket Fabrication Ast Group MS Glass substrate Real photo will be added here…. 1.No bonding between glass and Si piece rails 2.Free expansion and shrinkage 3.Controlling capillary phenomena

Fabrication Process of Si-Framed Pocket Si Pyrex Spacer (~ 500  m) Bottom of EV 501 Bonder Chamber Graphite chuck 120 N, 350 °C, 1000 V Positive bias Negative bias Si pieces (~ 300  m) Bottom of EV 501 Bonder Chamber Positive bias Si Ast Group

Vg(V) Vd(V) Base line Characteristics (TFT on Si Wafer, Thermal Anneal) Ast Group * W/L = 55um/8um * Channel Mobility  7 cm 2 /Vs * Poly-Si active layer: 620 ° C, 100nm * Gate oxide (LTO): 400 ° C, 100nm

LPCVD poly-Si TFT on the Glass Ast Group * Poly-Si active layer: 550 ° C, 100nm * Gate oxide (LTO): 400 ° C, 100nm * TFT was short after thermal anneal * 580C poly-Si active layer * 620C, 24 hrs * SIMS data

Ast Group SIMS Analysis Boron Si * After 620 ° C, 24 hrs anneal Boron diffused out from the glass ! * CTE mismatch caused thermal stress * Laser anneal was done instead of the conventional thermal anneal

XRD of Poly-Silicon (Thermal, Laser Anneal) (111) (220) (111) 500  C poly-Si on Glass 500  C on Glass after Laser Anneal at 283 mJ Ast Group

Characteristics (TFT on MS Glass, Laser Anneal) Ast Group

Summary and Future Plan 1. Fixture developed to process 2. Base 3. CVD poly 4. Laser recrystallized 5.According to SIMS analysis, boron diffused into poly-Si layer after thermal annealing of 620C, 24 hrs * Future Plan * 1.Better effective Hydrogenation 2.Improvement of characteristics by Recrystallization - Rapid Thermal Anneal (or standard anneal) - Ni catalyzed crystallization 3.Stress and bending test 4. Bending Ast Group

Acknowledgement CNF, a National Science Foundation supported National Nanofabrication Users Network (NNUN) Facility; Corning Inc.