Robust Low Power VLSI R obust L ow P ower VLSI Using Module Compiler to build FPGA Structures Seyi Ayorinde ECE 6505.

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Presentation transcript:

Robust Low Power VLSI R obust L ow P ower VLSI Using Module Compiler to build FPGA Structures Seyi Ayorinde ECE 6505

Robust Low Power VLSI Outline  Architectures  FPGA  Look-Up Table (LUT)  Configurable Logic Block (CLB)  Switch Box  Using Module Compiler  Approach  Challenges 2

Robust Low Power VLSI Architecture - FPGA 3

Robust Low Power VLSI Architecture - LUTs 4

Robust Low Power VLSI Architecture – CLB 5 For the purposes of this project, 1 BLE = 1 CLB (no clustering)

Robust Low Power VLSI Architecture – Connectivity to Interconnect 6

Robust Low Power VLSI Architecture – Switch Matrix 7

Robust Low Power VLSI Project Architecture  100 CLBs  10 x 10 Array  4-Input LUTs  No Clustering  Channel Width – 4  Reconfigurable Switch – Mux 8

Robust Low Power VLSI Mini-Example 9

Robust Low Power VLSI Approach  Module Compiler – Relative Placement  Places portions of the design in specific areas relative to each other  Uses a grid of rows and columns  (0,0) is bottom left corner 10

Robust Low Power VLSI Acronyms  HC and VC – Horizontal and Vertical Channels  SM – Switch Matrix  CLB – Configurable Logic Block 11

Robust Low Power VLSI Relative Placement for FPGA 12 SM (7,1) HC (7,2) SM (7,3) HC (7,4) SM (7,5) HC (7,6) SM (7,7) PAD (2,0 VC (6,1) CLB (6,2) VC (6,3) CLB (6,4) VC (6,5) CLB (6,6) VC (6,7) SM (5,1) HC (5,2) SM (5,3) HC (5,4) SM (5,5) HC (5,6) SM (5,7) PAD (2,0 VC10 (4,1) CLB (4,2) VC11 (4,3) CLB (4,4) VC (4,5) CLB (4,6) VC (4,7) SM10 (3,1) HC10 (3,2) SM11 (3,3) HC11 (3,4) SM (3,5) HC (3,6) SM (3,7) PAD (2,0) VC00 (2,1) CLB (2,2) VC01 (2,3) CLB (2,4) VC (2,5) CLB (2,6) VC (2,7) SM00 (1,1) HC00 (1,2) SM01 (1,3) HC01 (1,4) SM (1,5) HC (1,6) SM (1,7) (0,0)PAD (0,2) PAD (0,4) PAD (0,6)

Robust Low Power VLSI Relative Placement for FPGA 13 SM (7,1) HC (7,2) SM (7,3) HC (7,4) SM (7,5) HC (7,6) SM (7,7) PAD (6,0) VC (6,1) CLB (6,2) VC (6,3) CLB (6,4) VC (6,5) CLB (6,6) VC (6,7) SM (5,1) HC (5,2) SM (5,3) HC (5,4) SM (5,5) HC (5,6) SM (5,7) PAD (4,0) VC (4,1) CLB (4,2) VC (4,3) CLB (4,4) VC (4,5) CLB (4,6) VC (4,7) SM (3,1) HC (3,2) SM (3,3) HC (3,4) SM (3,5) HC (3,6) SM (3,7) PAD (2,0) VC (2,1) CLB (2,2) VC (2,3) CLB (2,4) VC (2,5) CLB (2,6) VC (2,7) SM (1,1) HC (1,2) SM (1,3) HC (1,4) SM (1,5) HC (1,6) SM (1,7) (0,0)PAD (0,2) PAD (0,4) PAD (0,6)

Robust Low Power VLSI Approach  Code has been written to:  Create and place CLBs  Create and place HCs and VCs  Create and place SMs while connecting to HCs and VCs  Connect CLB Output to each channel  Connect CLB Input to each channel  Code needs to be written to:  Create and place I/O Blocks 14

Robust Low Power VLSI Possible Issues  MCL Code  Demux function for connecting signal to multiple signals  If/else structure  Wire Directives (making sure vertical wires are vertical, etc.) 15

Robust Low Power VLSI (Immediate) Future Work  Add I/O Blocks  Debug Code 16

Robust Low Power VLSI Deliverables  MCL Code  Other MC Outputs  Layout file, Report Files, etc.  VHDL Code (Output of Module Compiler)  Schematic View  Layout (?)  Analysis of MC 17

Robust Low Power VLSI Questions? 18