M. Gilchriese WBS Pixel System DoE/NSF Review May 2003

M. Gilchriese 2 Cost Summary Includes items added via Baseline Change Proposals from Management Contingency(about $0.5M) in both preliminary and final ETC03 budgets.

M. Gilchriese 3 Milestones

M. Gilchriese 4 2-Hit System - US Deliverables Mechanics( ) –Support tube and patch pannels at end of support tube –Overall pixel support structure(frame) –Disks –Coolant pipes(shared with Europe) –Power and other cables(shared with Europe) –Tooling for final assembly of system(shared with Europe) Sensors( ) –About 20% of production procurement and testing Electronics( ) –About 20% production procurement, 50% of testing of front-end ICs –About 50% production procurement and testing of optical ICs –Common test systems for all collaboration for front-end ICs, modules Hybrids( ) –All flex hybrids –Optoboards procurement, shared assembly and testing Modules( ) –Thinning, dicing of FE and die sort –Assemble and test about 25% of modules Test Beam and System Tests( ) –Beam test support at CERN and systems tests in U.S.

M. Gilchriese 5 US Institutions and Management ALB LBL UNM UOK OSU Pixels(Gilchriese) Mechanics(Gilchriese, Anderssen) x Sensors(Seidel, Hoeferkamp) x Electronics(Einsweiler, Richardson) x x Hybrids(Skubic, Boyd, Gan) x x x Modules(Garcia-Sciveres, Goozen) x x Test Beam and System Test(Richardson) x (Physicist, Engineer ) SUNY Albany, LBL, New Mexico, Oklahoma, Ohio State In addition, off-detector electronics(ReadOut Drivers for both pixels and SCT) are separate project(Wisconsin, Iowa State and LBL).

M. Gilchriese 6 Since Last Review First 0.25  chips worked well enough so that decision was made in July 2002 to plan for accelerated production based on 2 nd iteration of chips. Production of front-end chips planned in two parts, roughly 20% and 80%. The “20%” order about to be delivered. Complete production fabrication for other ICs(module control and optical chips) also in progress. Production of the U.S. modules and deliverables (disks) in particular would start with these “20%” chips and receive priority in allocation of other components => start production of disks first. Other parts of the system – mechanics, sensors, hybrids – are completed, in production or in advanced design/prototypes.

M. Gilchriese 7 ATLAS Inner Detector Pixel System

M. Gilchriese Mechanics Disk Rings Endplate Endcone Disk Frame Barrel Frame Disk Ring Mounts Disk Sectors

M. Gilchriese 9 Global Support Frame Vendor fabrication is complete. At LBNL for survey, dry fit.

M. Gilchriese 10 Disk Support Rings Vendor fabrication is complete. Next step is trial insertion into frame

M. Gilchriese 11 Disk Sector Fabrication Major delay. Production had started October 2002 but then ATLAS changed it’s fault pressure specification from 8 bar to 16 bar => change aluminum alloy and process in coolant tube to reduce deformation. This was not easy but solution found. We are now back in production but have lost 6 months. Still can meet need(first production sector not required until October 2003).

M. Gilchriese 12 Pixels Installed LBNL responsible for tube and beam pipe support structures Services and Beam Pipe Support Structure SCT Barrel TRT Forward Side CSide A Services and Beam Pipe Support Structure Pixel Detector TRT Forward Beam Pipe Support Wire ID Endplug PP1 PST Support Flexures Insertion Trolley Beam Pipe Pixel Support Tube Package Insertion Riders Z=848 – Wire Support Z=3092 – PP1 Z=3120 – Adjustors PP1 Bellows/Temporary Support Z=~3200 – Bellows/Temp. Support

M. Gilchriese 13 Pixel Support Tube - I Backing Ring Flange Face Flange Asm Barrel Shell Barrel Shell with flanges barrel shell structural barrel shell w/ mount pads barrel shell w/ SCT Mounts 5 3 Hoop Element Hoop Stiffener Flat Rail V-Rail Mount Pad Insulator SCT Mount Block Asm SCT Mount Block

M. Gilchriese 14 Pixel Support Tube - II Production Readiness Review passed February Extensive prototypes fabricated at LBNL using autoclave. One-half production material ordered(limited shelf life) Production 3m mandrel about to arrive and all fabrication will occur at LBNL. Rails Foot long shell

M. Gilchriese 15 Service Panels FDR in June ‘03 Beam Pipe Support Structure Pixel Detector Not Shown Beam Pipe Service Panels PP1 Patch Panel(pipes and cables not shown!) PP0 Patch Panel

M. Gilchriese 16 Beam Pipe Support WBS 1.10 supported FDR passed 4/29/03 PRR will be 10/03 Wires at Z=-848,+848 Fixed Adjustors (no spring) Top and Side Sprung Adjustors Side and bottom (tension limiters) Wire Adjustors Cruciform supports Longerons Service panel Attachment points Adjustor Prototype

M. Gilchriese 17 Patch Panels Fabrication of prototypes of PP0 and PP1 underway. Mockup of PP1 region underway at CERN. PP0 Prototype Connectors Flex circuit glued to carbon-fiber support PP1 at End of Support Tube Beampipe Prototype Endplate

M. Gilchriese Sensors 4” wafer at right. Three “tiles” (one tile per pixel module) per wafer. Baseline plan is to split order(2000 total tiles) equally between two vendors. Four test sites New Mexico is US test site.

M. Gilchriese Sensors 240 wafers from one vendor(CIS) have been delivered and tested(60 at the Univ. of New Mexico). The contract specifies good tiles not wafers good tiles have been ordered so far from CIS and the 240 wafers have yielded about 600 good tiles. CIS will resume delivery in the next few months and the initial order should be complete by Fall this year. The 2 nd vendor, Tesla, has not been qualified for production. They have delivered a 2 nd series of preproduction wafers. Initial tests are positive, quality comparable to CIS, but additional studies(including irradiation) are underway. We expect to decide if Tesla is a production vendor next month. If they are, would order up to 1000 tiles. If not, order more from CIS, roughly 30% increased cost.

M. Gilchriese 20 Pixel Hybrids and Modules M. Garcia-Sciveres from LBNL is the overall ATLAS module coordinator, Schematic Cross Section (through here) Bumps Flex Hybrid Sensor Wirebonds ASICs Pigtail (beyond) To electrical-to- optical transition

M. Gilchriese 21 Module Assembly Flow

M. Gilchriese Electronics This includes the integrated circuits on the detector, test systems and testing and systems engineering. The U.S. continues to provide the overall coordination for the collaboration(K. Einsweiler). See separate talk on Read Out Drivers. Doric (from PIN diode to decoded LVDS) VDC array (from LVDS to laser diodes) Front End Chip 2880 channels Module Control Chip Manages data & control between module’s 16 chips Optical interface chips

M. Gilchriese 23 1 st 0.25  Chipset Two versions of FE-I1, MCC-I1, DORIC-I2 and VDC-I2 submitted Nov. ’01, received Feb. ’02. Basic functionality was good for all chips, no major errors in design. However, yield of FE and MCC was poor. IBM was very responsive in attempting to address problem(seen also in non- pixel chips) but in the end we just produced more wafers –Original 12 wafers had 15% yield for FE –Next 4 “backup” wafers had 3% yield –New lot 1(24 wafers) had yield of 70% for FE, 90% for MCC and was purchased. –2 nd new lot had yield of 25% for FE and few wafers purchased. These chips have been used to validate designs and build many prototype modules. Some example test results follow.

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M. Gilchriese 32 Module – not irradiated

M. Gilchriese 33 FE-I1 -> FE-I2 Improved threshold dispersion and control. Optimized preamp design for long and ganged pixels. Improved voltage distribution within pixel array to correct problem seen in FE-I1. Improved Single Event Upset(SEU) design. Optional auto-threshold tuning circuit which would allow tuning to be done more than a 1000 times faster. Fixed minor bugs All of this required moving from 5 metal to 6 metal layers. This plus schedule(MCC) and manufacturing considerations moved us to separate the FE and MCC+optical chip fabrications.

M. Gilchriese 34 Optical Chips Ohio State is responsible in US for both electronics design of optical chips (in collaboration with Germany) and opto-boards that hold the electronics and the optical packages(Taiwan). Small chips, can use multi-project runs. Successful irradiation of DORIC-I4 and VDC-I4 in Aug. ’02 – see some examples next pages Have recently received the optical chips from the fifth prototype run(multi-project run). Both the decoder (DORIC) and VCSEL driver (VDC) chips satisfy the specifications.

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M. Gilchriese 37 Production Status and Plan FE-I2 in production of concurrent 6-wafer engineering run and a 48-wafer production run. Submitted on April 4. 6-wafer order delivered to CERN last week and testing will start this week. 48-wafer out date is June 24. There are 288 potentially good die per wafer. Assuming a 50% yield, this is about 20% of required die. Assuming design OK, will likely order remainder in 48 wafer lots(ie. 4 of these) to mitigate potential IBM yield issues. MCC-I2 and optical IC run is a 6 wafer run with the option to purchase additional wafers up to maximum total of 12. Submitted on April 21. Potentially 536 MCC per wafer and 268 DORIC and VDC per wafer. If OK, and yield reasonable, this is final production run. If yield terrible but designs OK, would order 48 more wafers(120K total, US about 25K).

M. Gilchriese 38 Validation and Testing FE wafer probing is split between LBL and Bonn. Each site capable of 1-2 wafers per day, ready to go. So should be able to test 48 wafers in about a month – not limiting factor. MCC testing done commercially in Europe. Optical chips tested by OSU and in Siegen. Small number of wafers, ready to go. Obviously extensive lab validation of designs, ready to go. July irradiation of single FE-I2-detector assemblies and packaged MCC-I2. Irradiated assemblies into August SPS beam. August irradiation of optical ICs on optoboards. August/September high intensity run to simulate worst case for innermost layer. October irradiation of I2 modules. Assuming lab tests OK, we will plan for success and proceed with module fabrication for disks and pre-production for barrel before completing all beam tests. Electronics PRR in November to trigger remaining 80% FE production.

M. Gilchriese Hybrids - Flex University of Oklahoma(R. Boyd) is responsible for design, production oversight and assembly. Albany does HV testing bare flex have been ordered so far, additional will be ordered when yield is known better First deliveries of bare hybrids to Oklahoma just this month. Component loading will commence shortly. Testing protocols have been largely validated by many version 4.x prototypes.

M. Gilchriese 40 Flex Hybrid Work Flow

M. Gilchriese 41 Flex Assembly/Test at Oklahoma

M. Gilchriese 42 Work Flow at Albany

M. Gilchriese Optical Hybrids Ohio State(Gan) responsible for design. Had four prototype runs of opto-boards using FR-4 to keep up with changes in the chips and optical package designs. Have recently received the first BeO opto-boards(BeO is the production material, need good thermal conductivity). There are several open vias per board due to insufficient gold filling. After repairing the vias with wire-wrap wires, the opto-board operates properly with low PIN current threshold for no bit errors, mA. Therefore there is no error in the design. The vendor is refabricating the BeO boards and delivery is expected in a month. Have built several versions of the chip/opto-board test systems. OSU also built the electronics for all proton irradiations at CERN. Opto-link passed the FDR in February 2003.

M. Gilchriese 44 Opto-Board with PP0 + Type 0 Cables l data/clock from DORIC to VDC rerouted via PP0/Type 0 cables PP0 Type 0

M. Gilchriese 45 Optoboards System Built for 2002 Irradiation at CERN BeO optical board BER tester fibers wire-wrap wireVCSEL opto-packVDC-I5

M. Gilchriese Modules Included in this WBS are –Wafer thinning for(mostly) AMS(indium bump bonding) –Single-die probing after bumping and dicing –Module assembly and test –Module mounting on sectors Wafer thinning –Mechanical back-grinding process –Thinning and dicing in same firm allows thin wafer to be transferred from grinding chuck directly to dicing chuck without handling thinned wafer Can dice wafer even if it breaks during thinning. –8 indium-bumped 8” FE-I1 wafers thinned and diced. Only 2 chips lost to a crack during thinning. –1 solder-bumped 8” FE-I1 wafer thinned and diced. –Target thickness of 180um achieved with 10um tolerance.

M. Gilchriese 47 Modules continued All thinned and diced indium-bumped chips probed individually at LBL. –Single chip probe loss rate is small after learning period All bumps on these chips photographed during probing. 150 frames per chip, each frame looks like this:

M. Gilchriese 48 Module Assembly About a dozen modules have been assembled and tested at LBNL. Assembly done by tech with simple fixtures. Current assembly time, including wire bonding, is about 3 hours per module. Tested using common systems developed at LBNL for collaboration. Need to assemble about 250 modules for baseline detector, average of about 1 per day. Burn-in system under development.

M. Gilchriese 49 Prototype Modules FE-I1 and MCC-I1 chips have been used to assemble modules from both bump bonding vendors – IZM(solder) and AMS(indium). About 1.7 Mpixels as of early May. A significant focus of this activity is to push everyone faster towards production and debug the many steps. PDB is Production Database

M. Gilchriese Beam and System Tests Beam tests and plans already described. System tests started at the sector level. Performance of modules on sector  performance of individual modules. No evidence for much degradation so far – see next page. Tests also done with realistic cable plant(150m) and power supply system including regulators. Performance with realistic services is about same as with bench supplies. Systems tests will expand to more modules on sector and multiple sectors.

M. Gilchriese 51 Sector Testing

M. Gilchriese 52 Schedule Overview From now until end of 2003 –Validate electronics design –Begin disk module production –Continue or complete mechanics production In 2004 –Final FE production –Continue and complete disk module production –Mount modules on sectors, assemble disks –Nearly complete mechanics production –Begin work at CERN(support tube) In 2005 –Complete work in U.S. and ship to CERN –Assemble and test pixels on surface In 2006 –Complete surface assembly and test –Install into Inner Detector –Start commissioning

M. Gilchriese 53 Cost Overview About ½ of the $1M increase arises from less base program support. Remainder from variety of technical and schedule reasons, increased labor costs.

M. Gilchriese 54 Issues Technical –No major technical issues at this moment. –But clearly we await the delivery and testing of ICs in fabrication. Cost –Reduction of base program support has been major part of cost increase. Outlook for base program in FY04(and beyond) remains bleak. –Installation costs remain in overall contingency pool – see next page for profile. Schedule –Acceptance of U.S. proposal to accelerate disk production and the fabrication of many modules with 1 st generation chips has helped to mitigate delays in starting IC production. –Nevertheless the schedule remains tight in most areas, 2004 will be peak year, reserve contingency to help with problems.

M. Gilchriese 55 Installation Costs Costs are almost entirely manpower, all work at CERN. Critical mechanical engineer and senior techs familiar with mechanics and services. Systems electrical engineer responsible for testing DAQ and software.

M. Gilchriese 56 Summary Technical progress has been excellent. First demonstration that pixels can really meet LHC requirements completed by ATLAS, led by the U.S. No technical show stoppers at this time. Significant call on contingency made but within estimate. Schedule is tight but feasible.