C.Bohm, K.Jon-And Digitizer Status Tilecal Institute Meeting

C.Bohm, K.Jon-And Outline The TTCrx grounding problem The BCID readout problem Production time schedule

C.Bohm, K.Jon-And The TTC grounding problem Some missing ground connections on the TTC-rx gave rise to intermittent errors. Problem not discovered in Stockholm due to low read out rate of test bench. After grounding the open inputs the faults disappear. Action: 4 open inputs must be grounded on all boards A new Stockholm test bench is being built to discover these kind of errors

C.Bohm, K.Jon-And Action plan: Fix 700 not mounted boards. Print a modified pattern onto already manufactured boards using thick film techniques, then mount the boards as usual. Procedure should be verified within a week. Fix 1400 already mounted boards. A more difficult problem. Done partly at our institute in parallel with testing above 700 boards, partly by a vendor:

C.Bohm, K.Jon-And Repair plan of mounted boards 1. Desolder TTCrx from the boards. Done in our institute. Rather easy, 2 minutes per board (in total about 50 hours). 2.Remove solder. Done in our institute. More difficult, 6 minutes per TTCrx (in total about 140 hours). 3.Print grounding pattern on bottom of TTCrx. 30 seconds per board. Done by us at M A Kapslingsteknik. 4.Harden the conductive paste in a nitrogen oven. At Ericsson once per day. Done by M A Kapslingsteknik. 5.Reballing the TTCrx. 9 at a time into the oven. Done by M A Kapslingsteknik. 6.Remounting the TTCrx. Perhaps 10 minutes per board. Done by us in collaboration with SMD production, our mounting vendor (in total about 240 hours). Two persons at our institute work half time about 11 weeks.

C.Bohm, K.Jon-And BCID read out problems At the recent TileCal expert week it was found that the BCID readings were unreliable.  This was found to be due to set-up and hold time violations which occurred since the output timing of the TTCrx chip was changed between different batches.  In the electronics meeting 4 different remedies were suggested:  Change of a clock driver to a faster component (“driver solution”)  Resistor delay clk_des_1 (not preferred)  Capacitor delay clk_des_1 (not preferred)  Replace clk_des_1 with clk (“clock solution”)

C.Bohm, K.Jon-And Comparison of ”driver” and ”clock” solution ”Driver”-solution Recent tests indicate time budget is safe. Time margin in worst case w.r.t. TTCrx clock is 1.3 ns. Some more tests are needed, e.g. with LV and temperature variations. Clean easy ”patch” (change a component). New components have to be burnt-in and radiation tested. ”Clock”-solution Safe timing solution. Patch not as clean as for driver. Incompatible with Sthlm link interface used in Sthlm. Takes 1 month to change interface.

C.Bohm, K.Jon-And Tentative time schedules 3/3Decision of BCID solution ”Driver”-solution 14/3: 20 boards QC and sent to ”expert week”. 21/3: 20 boards to C-F if OK. 24/3: 20 ”printed” boards to C-F 14/4: 50 boards to C-F 21/4: 50 boards to C-F 28/4 … 100 boards per week. ”Clock”-solution” 7/3: 20 boards to ”expert week” before QC 11/4: 20 QC boards to C-F. 14/4: 20 ”printed” boards to C-F 5/5: 50 boards to C-F 11/5: 50 boards to C-F 18/5 … 100 boards per week. N.B. These are AGRESSIVE time schedules.