Enhancing the Area-Efficiency of FPGAs with Hard Blocks Using Shadow Clusters Peter Jamieson and Jonathan Rose

Modern FPGAs Consist of: 1.Programmable logic and routing soft logic cluster tile 2.Dedicated hard circuits e.g. multiplier tile e.g memory block tile

Fundamental FPGA Question Hard circuits provide benefit when used –Faster –Smaller –Consume less power

However… If not used Waste Area for Logic

However… If not used Waste Area for Logic Routing resources wasted!!! 70-90% of FPGA area occupied by routing

Improve Area-Efficiency of Hard Block Add flexibility so we can use hard circuit more often

Improve Area-Efficiency of Hard Block Add flexibility so we can use hard circuit more often Why not soft logic SHADOW CLUSTER

Example 1 FPGA has 1 mult. for every 4 pieces of soft logic Result is same for both shadow and non-shadow

Example 2 FPGA has 1 mult. for every 4 pieces of soft logic

Example 2 FPGA has 1 mult. for every 4 pieces of soft logic Here, shadow cluster FPGA is 2/3 the size

Notes Wins even though hard circuit with shadow cluster is slightly bigger! Benchmarks statistical demand for multipliers key –Average and Variance

One Interesting Result Virtex4 SX like FPGA with shadow clusters 7.5% smaller than without