Pipeline Processor Design Project Jarred Beck. Design Assumptions Three bit opcode This is to be able to address all of the 8k memory directly. 2 13 =

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Presentation transcript:

Pipeline Processor Design Project Jarred Beck

Design Assumptions Three bit opcode This is to be able to address all of the 8k memory directly = registers with some limitations In certain formats, only the first 8 are able to reached Two reserved registers for the lw and sw.

Design Assumptions Cont. Pipeline Data Path Structure Ease of testability. (theoretically) Fast. Compiler responsibility’s Hazard Prevention. Lw and Sw data moving. Jump return.

Register List RegisterRegister #Description $zero0 Holds constant zero value $a01 Holds an argument value $a12 Holds an argument value $a23 Holds an argument value $t04 Holds an argument value $t15 Holds a temporary value $s06 Holds a saved value $lr7 Last value loaded from memory $sr8 Last value stored into memory $s09 Holds a saved value $s110 Holds a saved value $t211 Holds a saved value $t312 Holds a saved value $ra13 Holds the return

Instruction Set Instruction Set Formats Inst. TypeFormat OpcodeResult Reg.Argument 1 Argument 2ALU Op Arithmatic (A)XXXXXXX XXXXX Opcode Compare Reg. 1 Compare Reg. 2Direction Branch Offset Branch (Br)XXX XXXXXXX OpcodeAddress Jump (J)XXXXXXXXXXXXXXXX OpcodeAddress Memory (M)XXXXXXXXXXXXXXXX

Instruction Set Cont. Opcode Instructions Arithmatic** Jump (J) Load Word (Lw) Store Word (Sw) Nop Hlt Beq Bneq ** has sub opcodes Instructions Add Sub And Or Beq Bneq j lw sw hlt nop

Control Unit 11 bits wide. Controls include Branch Flags Jump Flag Data Memory Read and Write Flags Register Write Flag Mux controls for Memory Input, Register Input, and Register Address

Control Unit Cont. Opcode Instructions Control Pattern Arithmatic** Jump (J) Load Word (Lw) Store Word (Sw) Nop Hlt Beq Bneq Control BitFunction 10Jump Flag 9BEQ Flag 8Data Read 7Data Write 6Data Select 5 Reg Write Sel. 4BNEQ Flag 3Reg Write 2PC Write 1 Branch Signal 0LW Addr Sel

Datapath

Simulation Results Individual Components All Components passed tests Datapath and CPU Datapath Passed tests Control Unit Passed test Memory passed Top level CPU problems

Moving Forward Debug Top level VHDL Altera passes compilation ModelSim gives error Synthesize corrected version into board

Questions? The End