Simulation-Based Verification of Microprocessor Units Based on Cycle-Accurate Contract Specifications Mikhail Chupilko, Alexander Kamkin, and Dmitry Vorobyev Institute for System Programming of RAS

SYRCoSE' May, 2008 Cost of microprocessor error Pentium FDIV Bug (Intel, 1994)  The cost is $ Phenom (9x00 Stepping B2) L3 Cache’s TLB Errata (AMD, 2007)  Implicit negative profit Design new microprocessor  The cost is about $

SYRCoSE' May, 2008 Levels of verification System-level verification Unit-level verification Test action Target system Test action Target system Target unit

SYRCoSE' May, 2008 Operation execution Operation Operands Time Clock Executing 1 st stage2 nd stage

SYRCoSE' May, 2008 Pipelined operations execution Operation A Operands Time Clock Executing A1 stageA2 stage Operation B Operands Executing B2 stageB1 stage Bubble

SYRCoSE' May, 2008 Contract specifications pre(input) // obligation for client output = operation(input) post(intput, output) // benefit for client If a client meets the precondition, then the component must fulfill the postcondition

SYRCoSE' May, 2008 Specification of operations Operation A Contracts of A ’s stages Contract of A A1A1 … ANAN guard(A 1 ) post(A 1 ) guard(A N ) post(A N ) … pre(A)

SYRCoSE' May, 2008 Idea of the approach post(A 2 )  post(B 1 ) Operation A Operation B A1A1 A2A2 …ANAN B1B1 B2B2 …BNBN Time Test Oracle 123 …

SYRCoSE' May, 2008 Requirements Requirement is a formal atomic predicate constructed on the defined functions. Types: Pre – req. on microoperation precondition Guard – req. on microoperation guard condition Update – implicit requirements on microoperation functionality Post – explicit requirements on microoperation functionality

SYRCoSE' May, 2008 Tool support The approach is integrated into the CTESK tool from the UniTESK toolkit Special library is developed to simplify the creation of specifications and tests for Verilog designs using CTESK

SYRCoSE' May, 2008 Specification example Floating-point adder Stage 0: alignment of exponent Stage 1: addition of fractions Stage 2: normalization of result

SYRCoSE' May, 2008 Catalogue example Operation ADD Stage 0Stage 1Stage 2Stage 3 pre[next cycle] alignment of exponent addition of fractions normalization of result

SYRCoSE' May, 2008 Precondition pre { return (isZero(op1) || isNormalized(op1)) && (isZero(op2) || isNormalized(op2)); }

SYRCoSE' May, 2008 Postcondition (for stage 3) post { return result == op1 + op2; }

SYRCoSE' May, 2008 Case study The approach was applied to several units of MIPS64-compatible microprocessor:  TLB (Translation Lookaside Buffer)  L2 Cache

SYRCoSE' May, 2008 TLB requirements PreGuardUpdatePostTotal Read50027 Write50229 Probe50038 Translate (Data) Translate (Instruction) Total

SYRCoSE' May, 2008 TLB verification results Specification consists 2.5 KLOC Labor-costs of testbench development is about 2.5 man-months We have found 9 errors

SYRCoSE' May, 2008 L2 cache requirements PreGuardUpdatePostTotal Load Loadi25029 Store Cache Load (DSP)10012 Store (DSP)10102 Total

SYRCoSE' May, 2008 L2 cache verification results Specifications consists 3 KLOC Labor-costs of testbench development is about 4 man-months We have found 6 errors

SYRCoSE' May, 2008 Future work Generalization for branching pipelines, pipelines with cycles, etc. Improvement of tool support for specification and tests development

SYRCoSE' May, 2008 Contacts Institute for System Programming of RAS UniTESK Technology Alexander Kamkin, Dmitry Vorobyev, Mikhail Chupilko { kamkin, vorobyev,

SYRCoSE' May, 2008 Thank You! Questions?