Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 18: More Complex Interfaces Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l HW#8 Due in 1 week l Proj#2 Due in 3 weeks

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Mentor Moment l When you lose, don’t lose the lesson l My first big failure » 1 year after my M.S. degree, I found myself responsible for a chip w/ 400,000 transistors and 4 engineers » It would have been a $50,000 paperweight, but it wasn’t heavy enough » I spent several months analyzing it to figure out what went wrong » What did I learn? –The importance of analyzing clock skew and checking timing constraints –My boss can make mistakes –I needed to be more forceful and polite in showing my peers how to avoid problems –People had more respect for me, rather than less, as I had feared

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Summary of Last Lecture l What procedure do we use to design an interface? » Specify Signals » Specify Protocol » Specify Other Details (“Loose Ends”) » Sample Waveforms » Draw Transmitter State-Transition Diagram » Write Transmitter Interface » Write Transmitter Test-Bench (Receiver Model) » Draw Receiver State-Transition Diagram » Write Receiver Interface » Write Receiver Test-Bench (Transmitter Model)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 Today’s Lecture l Flow Control Interfaces l Example 3: Transmitter » Module description » Test-bench l Example 4: Flow Control Receiver » Module description » Test-bench

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Review: Types of Interfaces l The interfaces we will discuss in this class will be differentiated in the following ways: » Response: Whether assertion of a coordinating signal receives a response » Initiator: Which module initiates the transfer » Control level: Whether the signal is coordinating the transfer of a single element of data or a block of data.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Flow Control l All the interface discussions so far have focused on control of the transfer of each element of data (word, byte). This is referred to as transfer control. l Additionally there may be a higher level of control which manages the transfer of blocks of data (e.g. messages). This control is referred to as flow control. l Flow control can be used in a number of ways to manage blocks of data. Some of these are: » Block Framing or Delimiting » Transfer Rate Control » Block transfer Initiation

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Interface with Flow Control l Signals » DATA: 8-bit data » msg_req: asserted to request a message » sending: asserted while a message is being sent » dready: one-cycle pulse when a byte is ready to transfer » dacpt: one-cycle pulse when the byte has been accepted AB DATA msg_req sending dready dacpt

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Interface with Flow Control l Protocol Specification: » All handshaking signals are initially low » When receiver is ready to receive a message, msg_req is raised. » Transmitter responds by raising sending » Transmitter puts data on DATA bus and puts a one- cycle pulse on dready » DATA remains valid until the receiver puts a one- cycle pulse on dacpt » Transmitter lowers sending when the last byte has been transferred. » Receiver lowers msg_req for at least one cycle

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 l Is the flow control » transmitter or receiver-initiated? » responsive or non-responsive » What is the responsive pair? l Is the transfer control » transmitter or receiver-initiated? » responsive or non-responsive » What is the responsive pair? Interface with Flow Control

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Interface Design Procedures » Specify Signals » Specify Protocol » Specify Other Details (“Loose Ends”) » Sample Waveforms » Draw Transmitter State-Transition Diagram » Write Transmitter Interface » Write Transmitter Test-Bench (Receiver Model) » Draw Receiver State-Transition Diagram » Write Receiver Interface » Write Receiver Test-Bench (Transmitter Model)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 Today’s Lecture l Flow Control Interfaces l Example 3: Transmitter » Module description » Test-bench l Example 4: Flow Control Receiver » Module description » Test-bench

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 Interface with Flow Control l Other Assumptions (Loose Ends): » Values will be read from / written to a memory array called nextdata » The number of bytes to send is in a signal called msgsize » A message will never be larger than 15 bytes » A message will always contain at least 1 byte

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 Interface Waveforms

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 Transmitter State Machine l Draw the portion of the state transition diagram for the transmitter

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 Transmitter Interface clock) case (state) TS1: if (!msg_req) sending=0; else begin addr=0; sending=1; state=TS2; end l Write the portion of the Verilog module that implements the transmitter interface

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 Transmitter Interface TS2: begin DATA=nextdata[addr]; $display($time," Transmitted %h",nextdata[addr]); addr=addr+1; dready=1; state=TS3; end

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 Transmitter Interface TS3: begin dready=0; if (dacpt) if (addr==msgsize) begin state=other; sending=0; end else state=TS2; else state=TS3; end endcase

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 Transmitter Test-Bench l Write the portion of the Verilog test-bench needed to test the transmit interface. See ex3.v on course web-site

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 Today’s Lecture l Flow Control Interfaces l Example 3: Transmitter » Module description » Test-bench l Example 4: Flow Control Receiver » Module description » Test-bench

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 Receiver State Machine l Draw the portion of the state transition diagram for the Receiver See ex4.v on course web-site

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 22 Different Implementations l What problem might you have with this implementation? l How could you fix this problem? l Does this solution create new problems?

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 23 Receiver Test-Bench l What should the receiver test-bench include?

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 24 Receiver Test-Bench l Write the portion of the Verilog test-bench needed to test the receive interface. See ex4.v on course web-site