Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 51 Lecture 5 Fault Modeling n Why model faults? n Some real defects in VLSI and PCB n Common fault models n Stuck-at faults n Single stuck-at faults n Fault equivalence n Fault dominance and checkpoint theorem n Classes of stuck-at faults and multiple faults n Transistor faults n Summary

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 52 Why Model Faults? n I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) n Real defects (often mechanical) too numerous and often not analyzable n A fault model identifies targets for testing n A fault model makes analysis possible n Effectiveness measurable by experiments

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 53 Some Real Defects in Chips  Processing defects  Missing contact windows  Parasitic transistors  Oxide breakdown ...  Material defects  Bulk defects (cracks, crystal imperfections)  Surface impurities (ion migration) ...  Time-dependent failures  Dielectric breakdown  Electromigration ...  Packaging failures  Contact degradation  Seal leaks ... Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 54 Observed PCB Defects Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 55 Common Fault Models n Single stuck-at faults n Transistor open and short faults n Memory faults n PLA faults (stuck-at, cross-point, bridging) n Functional faults (processors) n Delay faults (transition, path) n Analog faults n For more examples, see Section 4.4 (p ) of the book.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 56 Single Stuck-at Fault n Three properties define a single stuck-at fault n Only one line is faulty n The faulty line is permanently set to 0 or 1 n The fault can be at an input or output of a gate n Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults a b c d e f 1 0 g h i 1 s-a-0 j k z 0(1) 1(0) 1 Test vector for h s-a-0 fault Good circuit value Faulty circuit value

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 57 Fault Equivalence n Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches). n Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. n If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. n Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 58 Equivalence Rules sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 AND NAND OR NOR WIRE NOT FANOUT

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 59 Equivalence Example sa0 sa1 Faults in red removed by equivalence collapsing 20 Collapse ratio = =

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 510 Fault Dominance n If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. n Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list. n When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example. n In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set. n If two faults dominate each other then they are equivalent.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 511 Dominance Example s-a-1 F1 s-a-1 F All tests of F2 Only test of F1 s-a-1 s-a-0 A dominance collapsed fault set

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 512 Checkpoints n Primary inputs and fanout branches of a combinational circuit are called checkpoints. n Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 513 Classes of Stuck-at Faults n Following classes of single stuck-at faults are identified by fault simulators: n Potentially-detectable fault -- Test produces an unknown (X) state at primary output (PO); detection is probabilistic, usually with 50% probability. n Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentially- detectable fault. n Hyperactive fault -- Fault induces much internal signal activity without reaching PO. n Redundant fault -- No test exists for the fault. n Untestable fault -- Test generator is unable to find a test.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 514 Multiple Stuck-at Faults n A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. n The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3 k -1. n A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. n Statistically, single fault tests cover a very large number of multiple faults.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 515 Transistor (Switch) Faults n MOS transistor is considered an ideal switch and two types of faults are modeled: n Stuck-open -- a single transistor is permanently stuck in the open state. n Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage. n Detection of a stuck-open fault requires two vectors. n Detection of a stuck-short fault requires the measurement of quiescent current (I DDQ ).

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 516 Stuck-Open Example Two-vector s-op test can be constructed by ordering two s-at tests A B V DD C pMOS FETs nMOS FETs Stuck- open (Z) Good circuit states Faulty circuit states Vector 1: test for A s-a-0 (Initialization vector) Vector 2 (test for A s-a-1)

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 517 Stuck-Short Example A B V DD C pMOS FETs nMOS FETs Stuck- short (X) Good circuit state Faulty circuit state Test vector for A s-a-0 I DDQ path in faulty circuit

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 518 Summary n Fault models are analyzable approximations of defects and are essential for a test methodology. n For digital logic single stuck-at fault model offers best advantage of tools and experience. n Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. n Stuck-short and delay faults and technology- dependent faults require special tests. n Memory and analog circuits need other specialized fault models and tests.