Fast Synthesis of Clock Gating from Existing Logic Aaron P. Hurst Univ. of California, Berkeley Portions In Collaboration with… Artur Quiring and Andreas Kuehlmann Cadence Berkeley Labs IWLS 2007

Motivation Dynamic power consumption of clock network consumes 30-40% of total power in current designs  Every register clock input is switched every cycle A large fraction of these transitions can be avoided Clock gating inserts combinational logic on clock path to conditionally block switching  Capacitive load is “hidden” behind gates

Implementation G is the gating condition for the registers R 1 -R 3  The clock is not propagated when active Glitches in G may propagate without a latch clk G clk G R1R1 R2R2 R3R3 clk G clk G R1R1 R2R2 R3R3 Clock GateGlitch-Safe Clock Gate

Clock Gating Problem Problem: How to produce gating conditions that are… 1. Functionally correct 2. Meet timing and physical constraints 3. Result in maximal dynamic power savings 4. Require minimal additional area and power to generate Combinational versus sequential  Combinational gating conditions are functions of signals available within the same cycle This work addresses the combinational problem…

Previous Approaches Human effort  Worthwhile investment at architectural level  Automatic approaches are needed at netlist level Symbolic computation of gating functions Problem 1: Symbolic functional manipulation is not scalable Problem 2: Implementing required logic is unpredictable quality ? 01

New Algorithm Computation is scalable and bounded  Combining simulation and SAT-solving Existing logic is heavily reused  Contains difficulty of synthesis problem  Minimizes design perturbation

Let x be the set of combinational inputs (PIs and states) Given a register R  Let x R be its current state  Let F R (x) be its next state The register doesn’t switch when F R (x) = x R A function G is a valid combinational clock gating function for R if the validity condition is met Terminology G1 (x)G1 (x) G2 (x)G2 (x) G3 (x)G3 (x) G4 (x)G4 (x)

Nodes Assume existing logic network is some sort of DAG Each node in the network implements some function f  Can be used “for free”… less additional load and wiring Nodes of interest are collected for each register Not all pairs need to be enumerated. Constrained by… 1. Physical location 2. Timing information 3. Functionality 4. Potential power savings

Nodes: Constraints Timing Constraints Reason: gating condition must be available before clock Late-arriving signals are discarded discardedkept Physical Constraints Reason: length of clock gating nets Limit nodes to a local region around reg. R

Nodes: Pruning Multiple simulation vectors are pushed through circuit and node / register pairs are examined 1. Search for counterexamples to functional validity  If one is found, node is marked as proven invalid 2. Accumulate probabilistic information about the actual coverage of a gating function  Using size of Boolean ON-set not an effective estimate  If available, simulation traces reflective of actual operation

Nodes: Proving Functional validity of nodes must be conclusive Problem is formulated as Boolean satisfiability using a simple test structure Two powerful speed-ups 1. Solver can be run in incremental mode 2. Counter-examples can be used for further simulation g(x) FR(x)FR(x) R x xRxR SAT?

Nodes are merged together into disjunctive covers  A cover G is a set of nodes { f i }  Is valid gating function for register R iff all f i are valid for R Functional coverage of clock gate is increased with little additional hardware  Only an additional input is required on the AND-gate Covers f1 (x)f1 (x) f3 (x)f3 (x) f2 (x)f2 (x) G (x)

Information collected thus far…  Possible nodes for each register  Validity and probability Selecting gates is an instance of rectangle covering But… correlation between nodes is not known Split rectangle covering into two phases  Cover generation and selection  Redo simulation between to capture correlation Covers: Problem f1f1... f7f7 f 104 f 233 R4R4 R5R5 R 66...R 87 registers nodes Proven Unknown Disproven Functional Validity

Covers: Generation & Selection A heuristic is used generate interesting covers Problem is maximum set covering  NP-complete  Efficient heuristics exist  Problem instance is sparse Covers are greedily selected in order of power savings  Power cost of additional logic included Negative power savings are ignored 0.25 G1G1... G7G7 G 104 G 233 R4R4 R5R5 R R registers covers

There’s More… When clock is gated, register keeps its value. Its input is irrelevant  An observability don’t care (ODC) is produced In general, these are difficult to utilize in logic minimization A purely structural simplification can be applied Rule: Any immediate fanout of f can be rewired to a constant if its transitive fanout contains only registers gated by a cover containing f clk G clk G f  f 0

Results Procedure can be applied both pre- and post- mapping  Post-mapping includes physical and timing information  Pre-mapping exposes non-physical signals If useful for clock gating, mark to be mapped Preliminary experimental results: technology independent netlist without pair-wise compounds  Applied to OpenCores benchmarks  Pre-synthesized using ABC logic synthesis package  Implemented in OpenAccess / OpenAccess Gear

Results Average reduction in register switching: 14.4% Average reduction in size of circuit: 7.7%

Completed Next Steps Technology-dependent version New scheme for delaying SAT-based proof Creating new simple functions of existing nodes  Additional candidates for improving coverage G1 (x)G1 (x) G2 (x)G2 (x) G2(x)G2(x) G3(x)G3(x)

Future Next Steps Hierarchical Clock Gating Bounded sequential gating selection  Reaching forward, to identify more unobservable transitions  Reaching backward, to generate more signals clk G1G1 G2G2 G3G3 clk G1 clk G2 clk G3 xixi x i-1 x i-2 g(x i-2 ) clk clk G