Notes on visit to Rome 28/04/2014 Christian Joram Szymon Kulis Samir Arfaoui

Great welcome, enthusiastic team – 2 senior physicists (Stefano, Franz) – 3 students (1 new, 2 are done) – 2(?) electronic engineers We were shown a few presentations on – overall system design – software – operation Lab visit, demo of DAQ

S. Veneziano (designed by Rome team ≠ Omega evaluation board)

EASIROC + Zedboard

Only 1 EASIROC version from Omega External trigger – to externally trigger the chip we have to provide the hold signal (as a TTL signal) must be adjusted to come as the signal from slow shaper peaks alternatively, implement delay of the input if hold signal comes too late ADC sampling frequency: 2 MHz – affects multiplexing – “ultimate” readout rate: 2 / 32 = ~ 50 kHz Analogue probe output very useful – can select nodes to probe on the EASIROC, e.g. after preamp, after shaper, … Rome observed fragility of EASIROC input with bias voltage (70V), killed a chip – future PCB design may include choice between AC or DC coupling

ZedBoard – commercial, off-the-shelf – costs a few hundred euros – FPGA Zynq 7020 (with embedded ARM processor) Data packet transport rate: ~kHz – however a packet may contain many triggers Zero-suppression foreseen, not yet implemented Readout of several boards in parallel is on Rome's agenda, but not yet tested – Can use Gigabit Ethernet switch to connect to several boards – How can synchronisation be guaranteed? – How would one combine it e.g. with a beam telescope DAQ in a test beam? BUSY logic not yet implemented

What we would need to get started ? – ~10 PCBs with updated design from Rome (320 ch.) – all the on-board components, mounting at CERN workshop – 10 EASIROC chips (from Omega) – 10 ZedBoards (off the shelve, from industry) – Linux PC – DAQ software packages (from Rome) – FPGA firmware (from Rome) The software is quite well documented in 2 theses (1 in English, 1 in Italian)

S. Veneziano

Conclusions The FPGA based readout system of the EASIROC developed in Rome is very versatile and flexible (it was originally conceived for the readout of a PIN diode array) but also a relatively complex. Thanks to the embedded CPU the system contains lots of (currently unused) potential (e.g. zero suppression, online data processing, …). Used as a black box, the system could be operational at CERN in about 2- 3 months. The configuration of the EASIROC, the data acquisition and transfer require the interplay of a number of busses, protocols etc. This has been solved, but expert knowledge of the system will be needed in case of extensions or debugging. --> The Rome system of the EASIROC ASIC seems to have most of the functionality needed for the readout of a few 100 SiPM channels in a lab (source, cosmics) or test beam. Measurement of time needs to be studied. It's a viable solution provided that 1 or 2 persons familiarise themselves with the system to do debugging and adaptation work.