Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 20, 2013 MOS Transistor.

Slides:



Advertisements
Similar presentations
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 29, 2010 MOS Transistors.
Advertisements

Field Effect Transistor characteristics
Chapter 6 The Field Effect Transistor
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.
Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory
VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley –
Lecture 11: MOS Transistor
10/8/2004EE 42 fall 2004 lecture 171 Lecture #17 MOS transistors MIDTERM coming up a week from Monday (October 18 th ) Next Week: Review, examples, circuits.
Design and Implementation of VLSI Systems (EN1600) lecture07 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.
EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory
The metal-oxide field-effect transistor (MOSFET)
CSCE 612: VLSI System Design Instructor: Jason D. Bakos.
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004 from CMOS VLSI Design A Circuits and Systems.
11/3/2004EE 42 fall 2004 lecture 271 Lecture #27 MOS LAST TIME: NMOS Electrical Model – Describing the I-V Characteristics – Evaluating the effective resistance.
Week 8b OUTLINE Using pn-diodes to isolate transistors in an IC
Dr. Nasim Zafar Electronics 1 - EEE 231 Fall Semester – 2012 COMSATS Institute of Information Technology Virtual campus Islamabad.
Lecture 2: CMOS Transistor Theory
VLSI design Lecture 1: MOS Transistor Theory. CMOS VLSI Design3: CMOS Transistor TheorySlide 2 Outline  Introduction  MOS Capacitor  nMOS I-V Characteristics.
EE105 Fall 2007Lecture 16, Slide 1Prof. Liu, UC Berkeley Lecture 16 OUTLINE MOS capacitor (cont’d) – Effect of channel-to-body bias – Small-signal capacitance.
© Digital Integrated Circuits 2nd Devices VLSI Devices  Intuitive understanding of device operation  Fundamental analytic models  Manual Models  Spice.
Transistor Characteristics EMT 251. Outline Introduction MOS Capacitor nMOS I-V Characteristics (ideal) pMOS I-V Characteristics (ideal)
Metal-Oxide-Semiconductor Field Effect Transistors
Lecture 3: CMOS Transistor Theory
© 2012 Eric Pop, UIUCECE 340: Semiconductor Electronics ECE 340 Lecture 35 MOS Field-Effect Transistor (MOSFET) The MOSFET is an MOS capacitor with Source/Drain.
Qualitative Discussion of MOS Transistors. Big Picture ES220 (Electric Circuits) – R, L, C, transformer, op-amp ES230 (Electronics I) – Diodes – BJT –
ECE 342 Electronic Circuits 2. MOS Transistors
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 12: September 24, 2014 MOS Transistor.
EE213 VLSI Design S Daniels Channel Current = Rate of Flow of Charge I ds = Q/τ sd Derive transit time τ sd τ sd = channel length (L) / carrier velocity.
NOTICES Project proposal due now Format is on schedule page
Norhayati Soin 06 KEEE 4426 WEEK 7/1 6/02/2006 CHAPTER 2 WEEK 7 CHAPTER 2 MOSFETS I-V CHARACTERISTICS CHAPTER 2.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 28, 2011 MOS Transistor.
© Digital Integrated Circuits 2nd Devices Device Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A.
1 Slides adapted from: N. Weste, D. Harris, CMOS VLSI Design, © Addison-Wesley, 3/e, 2004 MOS Transistor Theory.
Qualitative Discussion of MOS Transistors. Big Picture ES230 – Diodes – BJT – Op-Amps ES330 – Applications of Op-Amps – CMOS Analog applications Digital.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 8: September 24, 2010 MOS Model.
Penn ESE370 Fall Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 5, 2011 Layout and.
CSCE 613: Fundamentals of VLSI Chip Design Instructor: Jason D. Bakos.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: August 30, 2013 Transistor Introduction.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 9: September 17, 2014 MOS Model.
Junction Capacitances The n + regions forms a number of planar pn-junctions with the surrounding p-type substrate numbered 1-5 on the diagram. Planar junctions.
UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: September 9, 2011 Transistor Introduction.
Device EE4271 VLSI Design Dr. Shiyan Hu Office: EERC 518
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: August 29, 2014 Transistor Introduction.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 12, 2011 Transistor Introduction.
Day 16: October 6, 2014 Inverter Performance
CMOS VLSI Design CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2007.
EE210 Digital Electronics Class Lecture 6 May 08, 2008.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 19, 2014 MOS Transistor.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 12: September 25, 2013 MOS Transistors.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 9: September 26, 2011 MOS Model.
MOSFET Current Voltage Characteristics Consider the cross-sectional view of an n-channel MOSFET operating in linear mode (picture below) We assume the.
Metal-oxide-semiconductor field-effect transistors (MOSFETs) allow high density and low power dissipation. To reduce system cost and increase portability,
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 11: September 22, 2014 MOS Transistor.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 14, 2011 Gates from Transistors.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 12, 2012 Transistor Introduction.
CP 208 Digital Electronics Class Lecture 6 March 4, 2009.
Introduction to CMOS VLSI Design CMOS Transistor Theory
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 5: September 8, 2014 Transistor Introduction.
Damu, 2008EGE535 Fall 08, Lecture 21 EGE535 Low Power VLSI Design Lecture #2 MOSFET Basics.
CMOS VLSI Design 4th Ed. EEL 6167: VLSI Design Wujie Wen, Assistant Professor Department of ECE Lecture 3A: CMOs Transistor Theory Slides adapted from.
The Devices: MOS Transistor
Day 9: September 27, 2010 MOS Transistor Basics
Day 10: September 26, 2012 MOS Transistor Basics
Qualitative Discussion of MOS Transistors
Day 2: September 10, 2010 Transistor Introduction
EMT 182 Analog Electronics I
Presentation transcript:

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 20, 2013 MOS Transistor Operating Regions Part 1

Today MOS Transistor Topology Threshold Operating Regions –Resistive –Saturation –Velocity Saturation –Subthreshold Penn ESE370 Fall DeHon 2

Last Time Penn ESE370 Fall DeHon 3

Depletion region  excess carriers depleted Penn ESE370 Fall DeHon 4 Refinement

Body Contact Fourth terminal Also effects fields Usually common across transistors Penn ESE370 Fall DeHon 5

No Field V GS =0, V DS =0 Penn ESE370 Fall DeHon 6

Apply V GS >0 Accumulate negative charge –Repel holes (fill holes) Penn ESE370 Fall DeHon

Channel Evolution Increasing Vgs Penn ESE370 Fall DeHon 8

Gate Capacitance Penn ESE370 Fall DeHon 9 Changes based on operating region.

Inversion Surface builds electrons –Inverts to n-type –Draws electrons from n + source Penn ESE370 Fall DeHon 10

Threshold Voltage where strong inversion occurs  threshold voltage –Around 2 ϕ F –Engineer by controlling doping (N A ) Penn ESE370 Fall DeHon 11

Resistive Region V GS >V T, V DS small Penn ESE370 Fall DeHon 12

Resistive Region V GS >V T, V DS small V GS fixed  looks like resistor –Current linear in V DS Penn ESE370 Fall DeHon 13

Linear (Resistive) Region Penn ESE370 Fall DeHon 14

Penn ESE370 Fall DeHon 15 Blue curve marks transition from Linear to Saturation Linear (Resistive) Region

Penn ESE370 Fall DeHon 16 Dimensions Channel Length (L) Channel Width (W) Oxide Thickness (T ox )

Preclass Ids for identical transistors in parallel? Penn ESE370 Fall DeHon 17

Preclass Ids for identical transistors in series? –(Vds small) Penn ESE370 Fall DeHon 18

Transistor Strength (W/L) Penn ESE370 Fall DeHon 19 S D

Transistor Strength (W/L) Shape dependence match Resistance intuition –Wider = parallel resistors  decrease R –Longer = series resistors  increase R Penn ESE370 Fall DeHon 20 S D

L drawn vs. L effective Doping not perfectly straight Spreads under gate Effective L smaller than draw gate width Penn ESE370 Fall DeHon 21

Channel Voltage Voltage varies along channel Think of channel as resistor Penn ESE370 Fall DeHon 22

Preclass 2 What is voltage in the middle of a resistive medium? –(halfway between terminals) Penn ESE370 Fall DeHon 23

Voltage in Channel Think of channel as resistive medium –Length = L –Area = Width * Depth(inversion) What is voltage in the middle of the channel? –L/2 from S and D ? Penn ESE370 Fall DeHon 24

Channel Voltage Voltage varies along channel If think of channel as resistor –Serves as a voltage divider between V S and V D Penn ESE370 Fall DeHon 25

Impact on Inversion What happens when –Vgs=2Vth ? –Vds=2Vth? What is Vmiddle-Vs? Penn ESE370 Fall DeHon 26

Channel Field When voltage gap V G -V x drops below V TH, drops out of inversion –Occurs when: V GS -V DS < V TH –What does this mean about conduction? Penn ESE370 Fall DeHon 27

Preclass 3 What is Vm? Penn ESE370 Fall DeHon 28

Channel Field When voltage gap V G -V x drops below V T, drops out of inversion –Occurs when: V GS -V DS < V T –What is voltage at Vmiddle if conduction stops? –What does that mean about conduction? Penn ESE370 Fall DeHon 29

Contradiction? Vg-Vx < Vt  cutoff (no current) No current  Vg-Vx=Vgs Vg-Vx=Vgs > Vt  current flows Penn ESE370 Fall DeHon 30

Way out? Vg-Vx < Vt  cutoff (no current) No current  Vg-Vx=Vgs Vg-Vx=Vgs > Vt  current flows Penn ESE370 Fall DeHon 31 Act like Vds at Vgs-Vt

Channel Field When voltage gap V G -V x drops below V T, drops out of inversion –Occurs when: V GS -V DS < V T –Channel is “pinched off” Penn ESE370 Fall DeHon 32

Channel Field When voltage gap V G -V x drops below V T, drops out of inversion –Occurs when: V GS -V DS < V T –Channel is “pinched off” –Current will flow, but cannot increase any further Penn ESE370 Fall DeHon 33

Pinch Off When voltage drops below V T, drops out of inversion –Occurs when: V GS -V DS < V T Conclusion: –current cannot increase with V DS once V DS > V GS -V T Penn ESE370 Fall DeHon 34

Saturation In saturation, V DS-effective =V x = V GS -V T Becomes: Penn ESE370 Fall DeHon 35

Saturation V DS > V GS -V T Penn ESE370 Fall DeHon 36

Penn ESE370 Fall DeHon 37 Blue curve marks transition from Linear to Saturation Saturation Region

Class Ended Here Penn ESE370 Fall DeHon 38

Switching Operation Consider Inverter Start with in=0V Output voltage? What does first-order model say about NFET? Penn ESE370 Fall DeHon 39

Switching Operation Input rises from 0V When cross into new region? What region cross into? Ids Current? What happens to Ids as V continues to rise? What is happening to Vout? Penn ESE370 Fall DeHon 40

Switching Operation Input at Vdd When NFET change operating regions? Which region move into? What’s happening to Vout? What region when settles to static voltage? Penn ESE370 Fall DeHon 41

Penn ESE370 Fall DeHon 42 Retrace Transition

Approach Identify Region Drives governing equations Use to understand operation Penn ESE370 Fall DeHon 43

Big Idea 3 Regions of operation for MOSFET –Subthreshold –Resistive –Saturation Penn ESE370 Fall DeHon 44

Admin Text – highly recommend read –Second half on Friday HW4 out –Get started over weekend Penn ESE370 Fall DeHon 45