TPC CRU Jorge Mercado (Heidelberg) Ken Oyama (Nagasaki IAS) CRU Team Meeting, Jan. 26, 2016

J. Mercado, K. Oyama 2 slide by C.Lippman Jan. 11, 2016

Readout options Current solution: 4 GBTs per FEC No FPGA on FEC No compression Up to 40 input links per CRU 4.48 Gbps wide-bus mode used in GBT Total data medium bandwidth to CRU: 40 x 4.2 = Gbps one CRU Reads from 10 FEC equivalent (1600 channel ADC) data  160 Gbps Implications No Huffman-like decoding needed in CRU (good) No deep buffers needed in CRU; data is well aligned in time (good) with compression, we need large buffer comparable or more of the largest Arria 10 Common mode noise reduction must be implemented in CRU (ok) 2D clustering is desired in CRU (as originally planned) J. Mercado, K. Oyama

J. Mercado, K. Oyama 4 slide by C.Lippman Jan. 11, 2016

TPC User Logic clock phase domain border GBT gearbox [0] CLK40 Data 80 CTRL 3 x20 half FECs 40 MHz x 80 bits 3.2 Gbps Assumptions 2560 data channels are divided into max.16 pad rows depending on node DSP chains (CF+DF) gives factor 4 compression factor 40 MHz x 10 bits x 100(avg.) ch = 40 Gbps Data Formatter [0] Data Formatter [1] 10 Gbps DSP[0] DSP[1] DSP[2] DSP[3] 20 Gbps 250 MHz x 256 bits (64 Gbps) PCIe E.P. [0] CLK250 Data 256 Async. FIFO [0] Async. FIFO [1] PCIe E.P. [1] Data 256 TTS gearbox CLK40 Data 192 PLL CLK10 CLK40 CLK250 CLK320 Avalon-MM Master Configuration Memory FEC Safety Module GBT SCA DCS Data Collector Last update Nov.24,2015 by K. Oyama exclusion handling GBT Fast Data Generator CLK40 CTRL 2 Data 80 common to all GBTs total throughput: 40 Gbps total bandwidth: 128 Gbps calibration manager ? top-level state-machine x16 rows timeframe buffers 4 x quad speed 160 ch. DSP chains (in: 40 Gbps/chain out: 10 Gbps/chain) BF: Baseline Filter GCF: Gain Correction Filter CMF: Common Mode Filter CF: Cluster Finder CMP: Compressor CMF [0] BF [0] GCF [0] CF [0] CMP [0] Core CRU Framework need multiple clock domain for different GBT links? CLK250 Sorting Matrix 40 or 80 MHz x 10 bits x 1600 ch (bandwidth) 10 MHz x 10 bits x 1600 ch = 160 Gbps (throughput) Channel Extractor [0,0] Async. FIFO [0] Stretch. [0] timeframe buffers (depth=4 case) 8Gbps Balanc e Switch row[0] J. Mercado, K. Oyama

6 GBT-FPGA Tx Arria 10 Resource Usage Synthesis (TX, GBT mode, Lat. Opt.): LC Combinationals: 234 LC Registers: 132 Block Memory Bits: 0 P&R: Combinational ALUTs: 234 Dedicated Logic Registers: 132 / 1.7M (0.0078%) M20Ks: 0 / 2713 (0 %) ALMs: 147 / 427K (0.034%) slide by Erno David on Jan. 19, 2016

7 GBT-FPGA Rx Arria 10 Resource Usage Synthesis (RX, GBT mode, Standard): LC Combinationals: 1136 LC Registers: 426 Block Memory Bits: 1280 P&R: Combinational ALUTs: 1136 Dedicated Logic Registers: 463 (???) / 1.7M (0.0027%) M20Ks: 4 / 2713 (0.15 %) (???) ALMs: 759 / 427K (0.18%) slide by Erno David on Jan. 19, 2016

Progress items Development framework (Erno, Johannes, Central CRU) Interface between common CRU and TPC user logic Git repository Build environment and infrastructure Working firmware with empty user logic 40 GBT input links, PCIe, AvalonMM Understanding the resources of the Arria 10 FPGA (Erno, Central CRU) Resource utilization of the “infrastructure” of the CRU (GBT cores, PCIe cores, DMA engine, etc.) and resources available for user logic Internal bandwidth of the data paths in the CRU Necessary & Achievable data reduction factor and outgoing PCIe bandwidth (Central CRU, O 2, and TPC-CRU) Developing user logic algorithms (TPC-CRU team) 2D cluster finder and common mode rejection (Torsten, Rourab) Channel extraction and sorting matrix (Masanori) SAMPA&GBT Data format (Sebastian, Christian) J. Mercado, K. Oyama