SOC Design Lecture 5 AMBA Signals. Youpyo DGU AMBA Bus Types.

Slides:

Advertisements

Similar presentations

On-Chip Communication Architectures

Advertisements

DATE 2003, Munich, Germany Formal Verification of a System-on-Chip Bus Protocol Abhik Roychoudhury Tulika Mitra S.R. Karri National University of Singapore.

IO Interfaces and Bus Standards. Interface circuits Consists of the cktry required to connect an i/o device to a computer. On one side we have data bus.

1 SoC (DSP+ARM) Platform SungKyunKwan University VADA Lab. ( )

ARM Based microcontrollers Asst. Prof. Dr. Alper ŞİŞMAN.

PRESENTER: PCLee System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores.

Computer Architecture

3D Graphics Content Over OCP Martti Venell Sr. Verification Engineer Bitboys.

FPGA Climatic Oana Valentina Rusu Advisor: Lecturer eng. Adrian-Vasile Duka PhD “Petru Maior” University of Tirgu Mures, Romania.

1 The 2-to-4 decoder is a block which decodes the 2-bit binary inputs and produces four output All but one outputs are zero One output corresponding to.

Digital Design Copyright © 2006 Frank Vahid 1 FPGA Internals: Lookup Tables (LUTs) Basic idea: Memory can implement combinational logic –e.g., 2-address.

Introduction to Avalon Interface Hardik Shah Robotics and Embedded Systems Department of Informatics Technische Universität München www6.in.tum.de 06 May.

Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Chapter 7 – Registers.

Reporter :LYWang We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication.

Lecture 4 Z80 Introduction Hong, You Pyo, DGU 1. Youpyo DGU Z80 Z80 is one of the most simple 8-bit microprocessor developed at 80’s. Z80 does.

1/1/ / faculty of Electrical Engineering eindhoven university of technology Processor support devices Part 1:Interrupts and shared memory dr.ir. A.C. Verschueren.

S&IP Consortium Course Material On-Chip Bus Speaker: Tian-Sheuan Chang July, 2004.

PradeepKumar S K Asst. Professor Dept. of ECE, KIT, TIPTUR. PradeepKumar S K, Asst.

1 EECS 373 Design of Microprocessor-Based Systems Prabal Dutta University of Michigan Lecture 5: Memory and Peripheral Busses September 21, 2010.

1 EECS 373 Design of Microprocessor-Based Systems Prabal Dutta University of Michigan Lecture 6: AHB-Lite, Interrupts (1) September 18, 2014 Slides developed.

SOC Design Lecture 6 HREQ and HGRANT. Kyungoh Park & Youpyo Hong, DGU Multi Master & Single Slave(MM & SS) Multiple masters cannot access the same slave.

Transaction Level Modeling with SystemC Adviser ：陳少傑教授 Member ：王啟欣 P Member ：陳嘉雄 R Member ：林振民 P

Memory II Computer Architecture and Design Lecture 4.

Overview Logic Combinational Logic Sequential Logic Storage Devices SR Flip-Flops D Flip Flops JK Flip Flops Registers Addressing Computer Memory.

Performance Analysis of Different Arbitration Algorithms of the AMBA AHB Bus Massimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, Claudio Turchetti.

Interfacing. This Week In DIG II  Basic communications terminology  Communications protocols  Microprocessor interfacing: I/O addressing  Port and.

CSE 140 Lecture 15 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.

COMP3221 lec31-mem-bus-II.1 Saeid Nooshabadi COMP 3221 Microprocessors and Embedded Systems Lectures 32: Memory and Bus Organisation - II

SOC Design Lecture 4 Bus and AMBA Introduction.

SOC Design Lecture 1 Overview of SOC.

Spring EE 437 Lillevik 437s06-l2 University of Portland School of Engineering Advanced Computer Architecture Lecture 2 NSD with MUX and ROM Class.

Computer System Configuration and Function Computer Architecture and Design Lecture 6.

1 EECS 373 Design of Microprocessor-Based Systems Prabal Dutta University of Michigan Lecture 5: Memory and Peripheral Busses September 20, 2011.

Dr. Rabie A. Ramadan Al-Azhar University Lecture 6

Logic Design Computer Architecture and Design Lecture 1.

CSC321 Where We’ve Been Binary representations Boolean logic Logic gates – combinational circuits Flip-flops – sequential circuits Complex gates – modules.

On Chip Bus National Taiwan University

Lecture 10 ALU and Control Unit Design Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU.

SOC Design Lecture 9 SRAM vs. NOR Flash. Taehyun Kim & Youpyo Hong, DGU SRAM vs. NOR Flash There are asynchronous SRAM and synchronous SRAM. Our SRAM.

Chap 7. Register Transfers and Datapaths. 7.1 Datapaths and Operations Two types of modules of digital systems –Datapath perform data-processing operations.

Chapter 6 FPGA Modules and Hardware Interface Design Professor Tzyy-Kuen Tien

I2C Master Core Simulation Environment. I2C Master Core Requirements Coverage (*) Requirement I2C IP RS-906: The I2C IP shall define the period of time,

Modes of transfer in computer

SOC Consortium Course Material On Chip Bus National Taiwan University Adopted from National Taiwan University SOC Course Material.

1 EECS 373 Design of Microprocessor-Based Systems Mark Brehob University of Michigan Lecture 12: Memory and Peripheral Busses October 22nd, 2013 Slides.

©2008 R. Gupta, UCSD COSMOS Summer 2008 Peripheral Interfaces Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.

Soc 5.1 Chapter 5 Interconnect Computer System Design System-on-Chip by M. Flynn & W. Luk Pub. Wiley 2011 (copyright 2011)

Computer Architecture Lecture – 4.  Discussed individual functional units of the computer.  But to form a fully computational unit, they must be connected.

CO5023 Latches, Flip-Flops and Decoders. Sequential Circuit What does this do? The OUTPUT of a sequential circuit is determined by the current output.

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 1 ECE 747 Digital Signal Processing Architecture SoC Lecture – Working with Buses & Interconnects.

SOC Design Lecture 2 Lecture Goal. YOUPYO HONG, DGU Our Final Goal in This Course is To Design AHB-compatible SRAM controller.

SOC Design Lecture 8 AHB-Based SRAM Controller. Youpyo DGU SRAM Controller Design Let’s design AHB-compatible SRAM Controller.

Aditya Dayal M. Tech, VLSI Design ITM University, Gwalior.

Presented By Aditya Dayal ITM University, Gwalior.

AMBA® 3 AHB-Lite Protocol

Slides developed in part by Mark Brehob & Prabal Dutta

Chapter 6 Input/Output Organization

ECE 4110–5110 Digital System Design

ME2100 EMBEDDED SYSTEM DESIGN (ARM9™) [Slide 8] ARM AMBA Bus BY DREAMCATCHER

Formal Performance Evaluation of AMBA-based System-on-Chip Designs

CSE 140 Lecture 15 System Designs

Lecture 10 Circuit Basics of Microprocessor

Lecture 14 Z80 Application Program

Lecture 15 Line Tracer Hong, DGU.

Burst read Valid high until ready high

SOC Design Lecture 4 Bus and AMBA Introduction.

CS 140 Lecture 16 Professor CK Cheng 11/21/02.

An IDP policy in Afghanistan What are the options?

Lecture 11 Z80 Instruction Hong DGU.

Presentation transcript:

SOC Design Lecture 5 AMBA Signals

Youpyo DGU AMBA Bus Types

Youpyo DGU Master and Slave Concept A can initiate a data transfer. (Write operation in this case.) B only responses to a A’s request. A is called a master and B is called a slave.

Youpyo DGU How about read operation? Which one is a master?

Youpyo DGU Bus Again In such simple case we do not need a bus.

Youpyo DGU AMBA for Multiple Masters & Slaves AMBA consists of Master, Slave, Arbiter, Mux, and Decoder. HADDR is the address from master to slave. HWDATA is the data from master to slave. HRDATA is the data from slave to master.

Youpyo DGU Number of Cases about BUS Single Master, Single Slave Multi Master, Single Slave Single Master, Multi Slave Multi Master, Multi Slave The Simplest BUS is the 1 st Case The last case should be a combination of 2 nd & 3 rd case.

Youpyo DGU Multi Master, Single Slave (MMSS) There’s a Mux. How do we make a “Master Selection” signal?

Youpyo DGU Arbiter When a master wants to transfer data, it sends a request signal to arbiter. If arbiter grants the request, then the master transfers data.

Youpyo DGU Single Master, Multi Slave (SMMS) There’s a Mux, but situation is different from MMSS case. How do we make a slave selection signal?

Youpyo DGU Decoder Slave A & B must have a different address. ex) Slave A : 0x0 ~ 0x3FFF, Slave B : 0x4000 ~ 0x7FFF Decoder decodes an address from master, and make a selection signal.

Youpyo DGU AMBA for Multiple Masters & Multiple Slaves

Youpyo DGU AMBA Signals SignalDescription HRESETReset HADDRAddress HWDATAData from master to slave HWRITEWrite Enable HRDATAData from slave to master HREADYIndicates slave is ready HREQUE STx Request from Master number x to Arbiter HGRANTxGrant from Arbiter to Master number x HSELxSection Signal from Decoder to Slave ……

Youpyo DGU What about human laws? There are millions of laws. Do you have to do all the legal actions everyday? No. You just need to do what you want. Just do not violate the laws. So, if you need a simple job, you can use a few AMBA signals only. Let’s find the “minimal set” of AMBA signal for our goal.

Youpyo DGU Single Master Single Slave (SM SS)

Youpyo DGU SM SS Write and Read HCLK HADDR HWRITE HWDATA

Youpyo DGU HW #2 (Due Next Class) List all possible combinations of timing for “Write” for SM SS situation. Which combinations violate AHB spec.? (Read AMBA Spec. and find out what kind of information is written on timing.) The goal of this HW is to distinguish the coverage of specification and implementation.