A.Nianin1 EMCal FEM noise study Goals: develope a mechanism to compute and store cell-dependent pedestals for zero-suppression in DSP’s; study the noise performance of existing FEM’s; develope a procedure which can be used for initial trouble- shooting of FEM’s on delivery; develope a standard or agreed “FEM certificate” acceptable to both the designers and physicists as a prerequisite for FEM being used for real data-taking.

A.Nianin2 Amplitude measurements in EMCal

A.Nianin3 Data Single file recorded near the end of engineering run (HV ON). Vref & Iref parameters loaded into individual ASIC boards selected to make full use of the available dynamic range (pedestals are close to 4000 counts). Data file contains events of three classes: laser pulses; pedestals; test pulse to photocell preamps What is presented - based upon pedestal events only.

A.Nianin4 FEM noise performance: Global RMS plot for HGRMS plot for low gain

A.Nianin5 High Gain leg - single cell noise High Gain Post, RMS multy-panel picture FEM 0 High Gain Post RMS FEM 1

A.Nianin6 High Gain Leg - cell dependent correlated noise FEM0FEM1

A.Nianin7 Low Gain Leg - single cell noise

A.Nianin8 Low Gain Leg - cell dependent correlated noise

A.Nianin9 TAC - cell dependent noise FEM0 FEM1

A.Nianin10 Pedestals - same cell in Pre and Post modes High Gain Low Gain Conclusion - pedestals for Pre&Post measurements are different

A.Nianin11 Pedestals - future strategy For all analysis purposes we will need to either compute the pedestals for every possible combination of a Pre&Post cells or to use pedestals computed for individual cells in Pre and Post modes. DSP software uses the second approach so we will most likely follow. Preferable software solution - reimplementing DSP as software preprocessor which will handle every event independently of its content prior to any tracing or physics analysis program. Reminder: zero suppression test Value(Post)-Ped(Post cell ) < Threshold

A.Nianin12 Pedestals - what is done for now Pedestals labeled by Post cell address were computed for every FEM channel - AMU Post cell combination. We looked for a pattern in the pedestal values in the FEM channel - AMU cell address plane. The expectations were that if pattern exists - it would signal the problem either with the actual design of FEM or timing problem in the FPGA code we are using now.

A.Nianin13 Pedestals - FEM 0 High gain Low Gain

A.Nianin14 Pedestals - FEM 1

A.Nianin15 Conclusions