Readout Control Unit of the Time Projection Chamber in ALICE Presented by Jørgen Lien, Høgskolen i Bergen / Universitetet i Bergen / CERN Authors: Håvard Helstrup – Høgskolen i Bergen; Dieter Röhrich, Kjetil Ullaland, Anders S. Vestbø – Univ. i Bergen; Bernhard Skaali, David Wormald – Universitetet i Oslo; Roberto Campagnolo, Luciano Musa – CERN for the ALICE Collaboration

ALICE TPC Read Out Chain In the pit In the counting room FECs incl. ALTRO RCU RORC incl PCI DDL DAQ

Basic operations of the RCU Configuration of ALTROs Read Out mode: –Reads out data from ALTROs after receiving triggers (Level2) on TTCrx. –Builds subevent in RCU memory. –Adds header information (trigger and orbit number, subevent size etc). –Sends data on DDL.

ALICE TPC Read Out TPC is split into subsectors with one DDL each (216 in total) DDL connected on the RCU One RCU collects data from up to 4500 channels (up to 25 FECards with 8 ALTROs each. Each ALTRO containing 16 Channels)

anode wire pad plane drift region 88  s L1: 5  s 200 Hz PASA ADC Digital Circuit RAM 8 CHIPS x 16 CH / CHIP 8 CHIPS x 16 CH / CHIP CUSTOM IC (CMOS 0.35  m) CUSTOM IC (CMOS 0.25  m ) DETECTOR FEC (Front End Card) CHANNELS (CLOSE TO THE READOUT PLANE) FEC (Front End Card) CHANNELS (CLOSE TO THE READOUT PLANE) PADS 1 MIP = 4.8 fC S/N = 30 : 1 DYNAMIC = 30 MIP CSA SEMI-GAUSS. SHAPER GAIN = 12 mV / fC FWHM = 190 ns 10 BIT < 10 MHz BASELINE CORR. TAIL CANCELL. ZERO SUPPR. MULTI-EVENT MEMORY L2: < 100  s 100 Hz DDL (3200 CH / DDL) Power consumption: ~ 40 mW / channel Power consumption: ~ 40 mW / channel gating grid ARCHITECTURE ALTRO

RCU Components The RCU is basically one big FPGA (for the number of pins) that communicates with: TTCrx (Trigger) DDL Link Card (DAQ) Front End Bus (Front End Electronics) Slow Control (Various testing and configuration)

Communication on the Front End Data Bus Uses a custom protocol sending ALTRO instructions from the RCU to the ALTROs on the FECs. –Can adress each channel one by one, or do broadcast. –Configure ALTRO (number of samples, multi-event buffer size etc.) –Read out channel by channel (RCU controls the Read and Write Pointers of the Multi-Event Buffers in the ALTRO) –During readout the ALTRO is pushing data into the RCU

DDL – The Detector Data Link Optical fibre, 100 MB/s, 32 bit wide databus DDL Link Card (CMC, mezzanine board) –Developed by KFKI-RMKI (Budapest) and CERN –Plugged as mezzanine board onto the RCU (CMC) –Custom protocol specified by the DDL group –Development of state machines and tests of read out of RCU to DDL done in collaboration with ALICE DAQ group at CERN

TTCrx – Trigger chip Delivering trigger information from the Central Trigger System (Level1 and Level 2 etc.) –Level1 and Level 2 is distributed to FECs from RCU Giving event tagging information which will be added to the event data on the RCU. (Orbit number, event number etc.) –The data header format to be used is an ALICE standard

Control Logics

RCU design – control flow State machines RCU resource & priority manager TTCrx FEE bus controller SIU controller DDL command decoder FEE SC DCS low level Watchdog 1: health agent Debugger PCI core Huffman encoder DCS high level Watchdog 2

Hardware

RCU Prototype II CONTROL LOGIC DDL – SIU PMC RCU PMCSRAM

Summary

Summary: RCU Hardware Development Prototype 1 used to test basic functionality Prototype 2 used to test different hardware options (memory buffers, DCS/Slow Control etc.) Final version will be optimised –only necessary components –fitted to TPC sector geometry

Summary: Logics Development All logics is developed in VHDL to be put in FPGA. –But transferrable to other technology. PCI core SIU-CMC interface SIU PCI bus FPGA internal SRAM memory FLASH EEPROM DCS Ether- net TTC rx FEE- bus DCS Profi- bus FEE SC

Local Controller DDL - INT Slow-Control Interface TTC-RX BOARD CTRL RCU Slow – Control (1 Mbit – serial link) Detector Link (100 MB / s) (#216) COUNTING ROOM Each TPC Sector is served by 6 Readout Subsystems Front-end bus (200 MB / sec) Local Slow- Control Serial link ON DETECTOR Overall TPC: 4356 Front End Card 216 Readout Control Unit FEC 128 ch Data Compr. GLOBAL ARCHITECTURE FEC 128 ch FEC 128 ch PASA – ADC – DIG. TPC FEE – OVERVIEW

End of presentation

Further Issues

RCU and SEU Use of SRAM-based FPGA necessitates special attention to the single event upset –Radiation tests are underway by the Budapest group (DDL Link card also uses FPGA) –Health tests will be included to monitor RCU functionality –Reconfiguration of RCU will be possible from onboard EPROMs or from external source All control logic will be written in VHDL -> Masked FPGA or Antifuse FPGA if needed.

RCU system for TPC sector readout test, Q1-2003: FEE-bus controller SIU controller PCI core SIU interface PCI bus FPGA SRAM LINUX RH7.2 FEE configurator PCI-tools RCU-API device driver SIU DIU interface PCI bus LINUX RH7.2 DATE 4 DDL/PCI-tools HLT-RORC- API device driver DIU DDL RCU prototype II RORC ext. SRAM FLASH Manager FEE- bus Trigger FEE-boards PCI core FPGA

MAX SAMPLING CLOCK 40 MHz MAX READOUT CLOCK 60 MHz 16-ch signal digitizer and processor HCMOS  m (ST) area: 64 mm 2 power: 16 mW / ch prototype delivery: Feb ‘ samples (4800 Ch) tested delivery of 4x10 4 chips: Dec ‘ bit 20 MSPS 11- bit CA2 arithmetic 18- bit CA2 arithmetic 11- bit arithmetic 40-bit format 40-bit format 10-bit arithmetic ALICE TPC READOUT CHIP (ALTRO) TPC FEE – OVERVIEW

The ALTRO chip on the Front End Card

RCU Prototype I Based on a commercial PCI board from PLDApplications Used for testing the basic ideas and readout of the ALTRO via PCI and DDL. –Mezzanine board connecting SIU and Front End Bus developed at CERN Expensive and not enough available pins to connect with all devices.

RCU Prototype II Custom development Includes the needed I/O-pins and SRAM Includes possibilities to test different hardware (par example DCS: Ethernet and Profibus) Mezzanine boards developed –FEBus Connectors and TTCrx –DDL Link Card

Design Methodology Development in Mentor Tools (FPGA Advantage, ModelSim) and ALTERA Quartus II Using behavioural models (VHDL or Verilog) as testbenches for development of state machines in logic (communicating with ALTRO, DDL, TTCrx, Slow Control etc.) All control logics are written in VHDL After simulating both for functionality and timing, tests are done in hardware (FPGA programmed)

TTCrx interface Firmware development –Model the TTCrx ASIC with VHDL –Emulate the TTC system stimulating the TTCrx model –Code the communication between the RCU FPGA and the TTCrx Trigger system test

Detector Control System Prototype II includes Profibus and Ethernet –Profibus for configuration and health checks and other low level applications –Ethernet for high level applications, like writing and reading registers Backend interface to DCS – OPC server

RCU design - data flow TTCrx registers Event memory 1 Event fragment pointer list TTC controller FEE bus controller Configuration memory FEE bus controller DCS SIU controller fifo SIU Huffman encoder Shared memory modules Event memory 2

RCU prototype II – mezzanine cards RCU Mezzanine Card Components on top side No maximum height restriction Front-End Bus Conn 1 Front-End Bus Conn 2 SIU mezzanine card (1/2 CMC)