Instructor: Alexander Stoytchev CprE 281: Digital Logic

Decoders and Encoders CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

Administrative Stuff HW 6 is out It is due on Monday (Oct 14) Wednesday (Oct 16)

Administrative Stuff HW 7 is out It is due next Monday (Oct 21)

Administrative Stuff Midterm Grades are Dues this Friday only grades of C-, D, F have to be submitted to the registrar’s office

Administrative Stuff Midterm Exam #2 When: Monday October 28. Where: This classroom What: Chapters 1, 2, 3, 4 and The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes).

Quick Review

Graphical Symbol for a 2-1 Multiplexer f s x 1 x [ Figure 2.33c from the textbook ]

Circuit for 2-1 Multiplexer f x 1 x 2 s f s x 1 x (c) Graphical symbol (b) Circuit [ Figure 2.33b-c from the textbook ] f (s, x 1, x 2 ) = s x 1 s x 2 +

4-to-1 Multiplexer: Graphical Symbol and Truth Table [ Figure 4.2a-b from the textbook ]

0 w 0 w w 2 w f 0 1 s 1 s Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer [ Figure 4.3 from the textbook ]

w 8 w 11 s 1 w 0 s 0 w 3 w 4 w 7 w 12 w 15 s 3 s 2 f 16-1 Multiplexer [ Figure 4.4 from the textbook ]

Synthesis of Logic Circuits Using Multiplexers

Implementation of a logic function with a 4x1 multiplexer [ Figure 4.6a from the textbook ] f w w fw 1 0 w 2 1 0

Implementation of the same logic function with a 2x1 multiplexer [ Figure 4.6b-c from the textbook ] (b) Modified truth table fw 1 0 w f w 2 w f w 1 w 2 w 2 (c) Circuit

The XOR Logic Gate [ Figure 2.11 from the textbook ]

The XOR Logic Gate

Implemented with a multiplexer f

The XOR Logic Gate Implemented with a multiplexer x y f

The XOR Logic Gate Implemented with a multiplexer x y f These two circuits are equivalent (the wires of the bottom and gate are flipped)

In other words, all four of these are equivalent! x y f x y f x y f f w w 2 1 0

Another Example (3-input XOR)

[ Figure 4.8a from the textbook ] Implementation of 3-input XOR with 2-to-1 Multiplexers w 1 w 2 w 3 f

[ Figure 4.8a from the textbook ] Implementation of 3-input XOR with 2-to-1 Multiplexers w 1 w 2 w 3 f w 2 w 3  w 2 w 3 

[ Figure 4.8 from the textbook ] Implementation of 3-input XOR with 2-to-1 Multiplexers (a) Truth table w 1 w 2 w 3 f w 2 w 3  w 2 w 3  f w 3 w 1 (b) Circuit w 2

w 1 w 2 w 3 f Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9a from the textbook ]

w 1 w 2 w 3 f w 3 w 3 w 3 w 3 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9a from the textbook ]

f w 1 w 2 (a) Truth table (b) Circuit w 1 w 2 w 3 f w 3 w 3 w 3 w 3 w 3 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9 from the textbook ]

Multiplexor Synthesis Using Shannon’s Expansion

w 1 w 2 w 3 f Three-input majority function [ Figure 4.10a from the textbook ]

w 1 w 2 w 3 f f w 1 Three-input majority function [ Figure 4.10a from the textbook ]

w 1 w 2 w 3 f f w 1 w 2 w 3 w 2 w 3 + Three-input majority function [ Figure 4.10a from the textbook ]

w 1 w 2 w 3 f (b) Circuit 0 1 f w 1 w 2 w 3 w 2 w 3 + f w 3 w 1 w 2 (b) Truth table Three-input majority function [ Figure 4.10 from the textbook ]

Three-input majority function f w 3 w 1 w 2

Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form:

Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form:

Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form: cofactor

Shannon’s Expansion Theorem (Example)

Shannon’s Expansion Theorem (Example) (w 1 + w 1 )

Shannon’s Expansion Theorem (Example) (w 1 + w 1 )

Shannon’s Expansion Theorem (In terms of more than one variable) This form is suitable for implementation with a 4x1 multiplexer.

Another Example

Factor and implement the following function with a 2x1 multiplexer

w f [ Figure 4.11a from the textbook ]

Factor and implement the following function with a 4x1 multiplexer

[ Figure 4.11b from the textbook ]

Yet Another Example

Factor and implement the following function using only 2x1 multiplexers

f g h w1w1

g 0 w3w3 w2w2 h w3w3 1 w2w2

Finally, we are ready to draw the circuit g 0 w3w3 w2w2 h w3w3 1 w2w2 f g h w1w1

g 0 w3w3 w2w2 h 1 f w1w1

w 2 0 w 3 1 f w 1 [ Figure 4.12 from the textbook ]

Decoders

2-to-4 Decoder (Definition) Has two inputs: w 1 and w 0 Has four outputs: y 0, y 1, y 2, and y 3 If w 1 =0 and w 0 =0, then the output y 0 is set to 1 If w 1 =0 and w 0 =1, then the output y 1 is set to 1 If w 1 =1 and w 0 =0, then the output y 2 is set to 1 If w 1 =1 and w 0 =1, then the output y 3 is set to 1 Only one output is set to 1. All others are set to 0.

Truth Table and Graphical Symbol for a 2-to-4 Decoder [ Figure 4.13a-b from the textbook ]

Truth Logic Circuit for a 2-to-4 Decoder [ Figure 4.13c from the textbook ]

Adding an Enable Input [ Figure 4.13c from the textbook ]

Adding an Enable Input [ Figure 4.13c from the textbook ] En

Truth Table and Graphical Symbol for a 2-to-4 Decoder with an Enable Input [ Figure 4.14a-b from the textbook ]

Truth Table and Graphical Symbol for a 2-to-4 Decoder with an Enable Input [ Figure 4.14a-b from the textbook ] x indicates that it does not matter what the value of these variable is for this row of the truth table

Graphical Symbol for a Binary n-to-2 n Decoder with an Enable Input [ Figure 4.14d from the textbook ] A binary decoder with n inputs has 2 n outputs The outputs of an enabled binary decoder are “one-hot” encoded, meaning that only a single bit is set to 1, i.e., it is hot.

How can we build larger decoders? 3-to-8 ? 4-to-16? 5-to-??

w 8 w 11 s 1 w 0 s 0 w 3 w 4 w 7 w 12 w 15 s 3 s 2 f Hint: How did we build a 16-1 Multiplexer [ Figure 4.4 from the textbook ]

w 2 w 0 y 0 y 1 y 2 y 3 w 0 En y 0 w 1 y 1 y 2 y 3 w 0 y 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1 A 3-to-8 decoder using two 2-to-4 decoders [ Figure 4.15 from the textbook ]

w 2 w 0 y 0 y 1 y 2 y 3 w 0 En y 0 w 1 y 1 y 2 y 3 w 0 y 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1 A 3-to-8 decoder using two 2-to-4 decoders [ Figure 4.15 from the textbook ] What is this?

w 0 y 0 y 1 En What is this?

A 4-to-16 decoder built using a decoder tree [ Figure 4.16 from the textbook ]

Let’s build a 5-to-32 decoder

Demultiplexers

1-to-4 Demultiplexer (Definition) Has one data input line: D Has two output select lines: w 1 and w 0 Has four outputs: y 0, y 1, y 2, and y 3 If w 1 =0 and w 0 =0, then the output y 0 is set to D If w 1 =0 and w 0 =1, then the output y 1 is set to D If w 1 =1 and w 0 =0, then the output y 2 is set to D If w 1 =1 and w 0 =1, then the output y 3 is set to D Only one output is set to D. All others are set to 0.

A 1-to-4 demultiplexer built with a 2-to-4 decoder [ Figure 4.14c from the textbook ]

A 1-to-4 demultiplexer built with a 2-to-4 decoder [ Figure 4.14c from the textbook ] output select lines the four output lines data input line D

Multiplexers (Implemented with Decoders)

w 1 w 0 w 0 En y 0 w 1 y 1 y 2 y 3 w 2 w 3 f s 0 s 1 1 A 4-to-1 multiplexer built using a 2-to-4 decoder [ Figure 4.17 from the textbook ]

Encoders

Binary Encoders

2 n inputs w 0 w 2 n 1– y 0 y n1– n outputs A 2 n -to-n binary encoder [ Figure 4.18 from the textbook ]

(b) Circuit w 1 w 0 y 0 w 2 w 3 y w 3 y 1 0 y w w w (a) Truth table [ Figure 4.19 from the textbook ] A 4-to-2 binary encoder

Priority Encoders

d w 0 y 1 d y z 1 x x 0 x w x 0 x w x w [ Figure 4.20 from the textbook ] Truth table for a 4-to-2 priority encoder

Questions?

THE END