Re-configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-micron Instructions Bus Siu-Kei Wong and Chi-ying Tsui

2/18 Outline Introduction Bus model and embedded system model Overview of the encoding scheme Static bus encoding scheme Dynamic bus encoding scheme Experimental results and comparison Conclusions

3/18 Bus model and embedded system model Bus model Cc: cross coupling capacitances Cs stand-alone capacitances Y: Cross coupling switching X: Bit lines switching

4/18 Bus model and embedded system model (cont.) i: bit line, j: cycle j X ij = 1, when there is an 0 to 1 transition 0, otherwise

5/18 Bus model and embedded system model (cont.)

6/18 Overview of the encoding scheme Reduce instruction bus energy Encoding instructions during compilation Off-line (static or dynamic encoding) Decoding information attached to program Load decoding information into lookup table Using decoding information when executing

7/18 Static bus encoding scheme Phase one Invert a set of bit lines Problem formulation Graph optimization problem

8/18 Static bus encoding scheme Phase two Rearranging the order of the bit lines Graph optimization problem Completely-connected undirected graph Traveling salesmen problem

9/18 Static bus encoding scheme Required overhead Extra bus transition activity 32log with 6 cycles 32 bits mux-based crossbar Inverting back the flipped bit lines Required hardware Crossbar for rearranging bit lines Inverters for inverting back bit lines A set of registers

10/18 Dynamic bus encoding scheme Encoding strategy Multiple permutations are generated Two strategies Phase two of static bus encoding The number of permutations is based on the number of blocks in the cache One permutation for one block

11/18 Dynamic bus encoding scheme Decoding strategy

12/18 Dynamic bus encoding scheme Overhead required Sending m sets of decoding information 32log 2 32 with 5m cycles Additional hardware for decoding Lookup table and crossbar Reduced dynamic encoding k groups where k=32/n

13/18 Experiment result ARM processor architecture 32 bits bus 20 mm for memory 15mm for cache 0.07 um technology with 1V power supply Three different cache block sizes

14/18 Experiment result Results of the static encoding scheme

15/18 Experiment result Results of the dynamic encoding scheme

16/18 Experiment result Comparison with previous work

17/18 Experiment result

18/18 Conclusions Both static and dynamic encoding Software-encoding During compilation time Good experiment result