President UniversityErwin SitompulDigital Systems 4/1 Lecture 4 Digital Systems Dr.-Ing. Erwin Sitompul President University

President UniversityErwin SitompulDigital Systems 4/2 Terms in Digital Logic Design Synthesis: the design of a new circuit that implements a desired function and behavior. Analysis: the task of determining the function and behavior of an existing circuit. LectureDigital Systems

President UniversityErwin SitompulDigital Systems 4/3 Example of Synthesis Given the following truth table, design the circuit LectureDigital Systems From the truth table, we now write the Sum-of-Product: Y 1 = A’B’ + A’B + AB We can now create the logic circuit: ● 1 st possibility

President UniversityErwin SitompulDigital Systems 4/4 LectureDigital Systems Example of Synthesis We can simplify the Boolean expression and obtain different synthesis result: Y 2 = A’B’ + A’B + AB Y 2 = A’(B’ + B) + AB(Distributive) Y 2 = A’ + AB(Complement) Y 2 = A’ + B(Elimination) ● 2 nd possibility

President UniversityErwin SitompulDigital Systems 4/5 Logic circuits should be implemented by using as few as logic gates as possible. Optimal implementation will directly affect speed, resource, and power consumption. One formula of how to calculate cost is: Cost = Σ(gates) + Σ(gate inputs) From previous pages, Cost of Y 1 = = 17 Cost of Y 2 = = 5 Minimum Cost Realization LectureDigital Systems

President UniversityErwin SitompulDigital Systems 4/6 Minimum Cost Realization Neither SoP nor PoS guarantee a minimum cost implementation. In stead of these two-level forms, in some cases a multi-level form is better. In practice, any circuit can be implemented only by using NAND and NOR Gates. NAND and NOR Gates provide higher speed, require less power, and can be built with less number of transistors. LectureDigital Systems Nevertheless, SoP and PoS are the basis for development of circuit minimization methods. Converting from SoP and PoS to NAND and NOR circuits is straightforward and easy.

President UniversityErwin SitompulDigital Systems 4/7 Minimum Cost Realization LectureDigital Systems A formula to calculate cost may include the following factors: Number of gates Number of gate inputs Number of transistors Area of the circuit Routing / wiring cost Critical path delay Minimum cost realization can be done by using several methods: Boolean algebra simplification Karnaugh map Quine-McCluskey algorithm NAND/NOR equivalent

President UniversityErwin SitompulDigital Systems 4/8 Example: Minimum Cost Realization LectureDigital Systems

President UniversityErwin SitompulDigital Systems 4/9 LectureDigital Systems Functional Completeness A set of Boolean operators is called functionally complete if the set can be used to express all possible logic functions by combining members of the set. Some sets of logic operators with functional completeness are: AND and NOT OR and NOT NAND NOR

President UniversityErwin SitompulDigital Systems 4/10 NAND and NOR Gates LectureDigital Systems ● NAND Gates ● NOR Gates

President UniversityErwin SitompulDigital Systems 4/11 NAND and NOR Gates: Inverter LectureDigital Systems ● Check the truth table of the (tied-together 2-input NAND and NOR Gates ? X X X

President UniversityErwin SitompulDigital Systems 4/12 NAND and NOR Gates: De Morgan’s Theorem LectureDigital Systems X Y X Y X Y X Y X Y X Y (X · Y)’ = X’ + Y’ (X + Y)’= X’ · Y’ ● NAND Gates ● NOR Gates

President UniversityErwin SitompulDigital Systems 4/13 Completeness of NAND Gate Any Boolean function can be implemented using NAND Gates only. NOT Gate  NAND Gate, with 2 inputs tied together. AND Gate  NAND Gate, followed by NOT Gate OR Gate  NAND Gate, preceded by NOT Gates LectureDigital Systems

President UniversityErwin SitompulDigital Systems 4/14 Completeness of NOR Gate LectureDigital Systems Any Boolean function can be implemented using NOR Gates only. NOT Gate  NOR Gate, with 2 inputs tied together. OR Gate  NOR Gate, followed by NOT Gate AND Gate  NOR Gate, preceded by NOT Gates

President UniversityErwin SitompulDigital Systems 4/15 Using NAND Gates to Implement an SoP LectureDigital Systems x 1 x 2 x 3 x 4 x 5 x 1 x 2 x 3 x 4 x 5 x 1 x 2 x 3 x 4 x 5

President UniversityErwin SitompulDigital Systems 4/16 Using NOR Gates to Implement a PoS LectureDigital Systems x 1 x 2 x 3 x 4 x 5 x 1 x 2 x 3 x 4 x 5 x 1 x 2 x 3 x 4 x 5

President UniversityErwin SitompulDigital Systems 4/17 Example: Realization with NAND Gates LectureDigital Systems For the following SoP circuit, make a circuit realization that only uses NAND Gates. x1x1 x3x3 x2x2 F F x1x1 x3x3 x2x2 F x1x1 x3x3 x2x2

President UniversityErwin SitompulDigital Systems 4/18 F x1x1 x3x3 x2x2 Example: Realization with NOR Gates LectureDigital Systems For the following PoS circuit, make a circuit realization that only uses NOR Gates. F x1x1 x3x3 x2x2 F x1x1 x3x3 x2x2

President UniversityErwin SitompulDigital Systems 4/19 Example: Realization with NAND Gates LectureDigital Systems For the following circuit, make a circuit realization that only uses NAND Gates. F x1x1 x3x3 x2x2 F x1x1 x3x3 x2x2 F x1x1 x3x3 x2x2 ● Redo this example for the use of NOR Gates ?

President UniversityErwin SitompulDigital Systems 4/20 LectureDigital Systems Exercise: SoP with NAND Gates Implement the following SoP function with NAND Gates only. F = Y’Z + X’YZ Try the variance where a)3-input NAND Gates are allowed b)only 2-input NAND Gates are allowed

President UniversityErwin SitompulDigital Systems 4/21 LectureDigital Systems Exercise: XOR with NAND and NOR Gates Implement the XOR Gate using NAND Gates only and NOR Gates only. Hint: Start from the truth table. ● Be sure to know the ways A

President UniversityErwin SitompulDigital Systems 4/22 Circuit A Homework 4 1.Implement circuit A with NAND Gates only and NOR Gates only. LectureDigital Systems Deadline: Wednesday, 14 October Circuit B 2.Implement circuit B with NAND Gates only and NOR Gates only.