FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Spring 2007 Instructor: Dr. Michael Frank Module #10: Sequential Logic Timing & Pipelining

FAMU-FSU College of Engineering Sequential Logic Timing Parameters  Any sequential storage element is subject to constraints on the relative timing of input, clock and output events.  Some important terms: Setup time t s – Min. req. time fr. start of valid input data to latching clock edge. Hold time t h – Min. req. time fr. latching edge to end of valid input data. Ouput delay time t od – Worst-case time from latching clock edge to first appearance of corresp. valid output data.  A.k.a. “Clock-to-Q” time  These parameters, together w. combinational propagation delays, determine the max. tolerable operating frequency for a given sequential circuit. clk D Q D valid invalid Q tsts thth t od Example: Rising edge- triggered D flip-flop new value old value

FAMU-FSU College of Engineering Estimation of Timing Parameters  Given the internal structure of a storage element, and the delays associated with its internal components, we can estimate its overall setup, hold, and output delay times. Example: Given that the prop. delay for NOT=1 ns, and NAND=2 ns, estimate t s, t h, and t od for the master-slave D flip-flop shown below. D D latch SR latch clk Q q ~q ~D ~r 1 ~s 1 ~s 2 ~r 2 ~clk Rising-edge-triggered D flip-flop made of a clocked D latch driving a clocked SR latch, w. negative clock skew to reduce output delay clk ~clk D ~D ~r 1 ~s 1 q ~q ~s 2 ~r 2 Q SR held SR transparent SR held SR transp. D transp. D held D transparentD held d1d1 undef. d2d2 ud. ~d 1 undef. ~d 2 d1d1 undef.und. ~d 1 d2d2 ~d 2 1 undef. 1 und. d1d1 undef. und. ~d 1 undef. 1 1 u u ~d 1 uu d1d1 d0d0 d1d1 d2d2 u u (Timing estimations on next slide)

FAMU-FSU College of Engineering Setup/Hold Time Estimations for this Example  Setup time t s = 4 ns, because Path to set D latch B+D+F+E (7 ns) must beat lockdown signal A+C&A+D (3 ns).  Hold time t s = 3 ns, because A+C (3 ns) must finish before it’s safe to allow D to fluctuate  Output delay t od = 7 ns, because Critical path is B+D+F+H+J+I (11 ns), minus setup time of 4 ns before clock edge D D latch SR latch clk Q q ~q ~D ~r 1 ~s 1 ~s 2 ~r 2 ~clk clk ~clk D ~D ~r 1 ~s 1 q ~q ~s 2 ~r 2 Q SR held SR transparent SR held SR transp. D transp. D held D transparentD held d1d1 undef. d2d2 ud. ~d 1 undef. ~d 2 d1d1 undef.und. ~d 1 d2d2 ~d 2 1 undef. 1 und. d1d1 undef. und. ~d 1 undef. 1 1 u u ~d 1 uu d1d1 d0d0 d1d1 d2d2 u u A B C D E F G H I J

FAMU-FSU College of Engineering Sequential Logic Timing Analysis  What is the minimum clock period t per,min and max freq. f max for this sequential circuit?  One constraint: New state D′ must be ready by at least a setup-time prior to next edge.  t per > t od + t pd + t s  Thus t per,min = t od + t pd + t s, and so f max = 1/(t od + t pd + t s ). Combinational state-update logic w. prop. delay t pd DQ t s, t h, t od clk D valid invalid Q tsts thth t od D′ tsts thth t pd

FAMU-FSU College of Engineering Why is Hold Time important?  Consider the behavior of a sequential circuit immediately after a clock edge… If the minimum (fastest-case) output delay plus propagation delay is less than the storage element’s hold time,  The flip-flop’s input can get corrupted before we are finished locking its state! The new-state signal “races” all the way around the circuit and interferes with itself.  This is an example of a “race condition” hazard. These can be avoided entirely by using “two- phase non-overlapping clocks” (next slide) Combinational state-update logic w. prop. delay t pd DQ t s, t h, t od D′ A race condition exists if t od + t pd < t h.

FAMU-FSU College of Engineering Two-Phase Non-overlapping Clocks  Suppose that the two latches making up a flip-flop are driven by independent clocks… That is, the 2 nd is not simply the complement of the first…  If the duty cycles (active periods) of the clocks are non-overlapping, then both latches are never transparent at the same time  For there to be a race condition is then impossible! latch 1 latch 2 next-state logic Φ1Φ1 Φ2Φ2 Φ1Φ1 Φ2Φ2 period of non-overlap latch 1 transparent latch 2 transparent

FAMU-FSU College of Engineering Generating two-phase nonoverlapping clocks from single-phase clocks  What if two-phase non-overlapping clocks aren’t provided to you? Never fear, you can make them with a NOR- based structure, like an unclocked SR latch…  The falling edge on one of the clock outputs causes a subsequent rising edge on the other… clk Φ1Φ1 Φ2Φ2 clk′ clk clk′ Φ1Φ1 Φ2Φ2

FAMU-FSU College of Engineering Clock Frequency Dividers  What if the available clock signals are too fast for your design, and you need a slower clock? This is easy, just use an n-bit counter to divide the input clock frequency by 2 n … You can also use a modulo-m counter with its overflow bit clocking a T flip-flop to obtain a frequency reduction by any even factor 2m. n-bit counter clk (freq. f) … q0q0 q1q1 q2q2 q n-1 frequency f/2 frequency f/4 frequency f/8 frequency f/2 n

FAMU-FSU College of Engineering Another way to generate 2-phase non-overlapping clocks  Assuming that you already have a working edge- triggered sequential counter… This method generates non-overlapping output clocks with frequencies ¼ that of the input clock.  Note there is also a significant period of non-overlap. Nearly eliminates possibility of race conditions. 2-bit counter t 1..0 decoder Φ1Φ1 e0e0 e1e1 e2e2 e3e3 Φ2Φ2 clk

FAMU-FSU College of Engineering JK Flip-Flops  A JK latch or flip-flop is like an SR flip-flop (with J=set, K=reset), but… When both J and K inputs are on, toggles (complements) the flip- flop’s state  This input combination was disallowed for the SR case  An (unclocked or level-sensitive) JK latch is not very useful because its output (when J=K=1) is unstable, and hence unpredictable. Move slide to earlier module Edge-triggered JK flip-flop from an edge-triggered D flip-flop J K Q D ck

FAMU-FSU College of Engineering T (Toggle) Flip-Flop  Basically, a JK flip-flop where J=K=T. When T is on, output is toggled  when T is off, output remains unchanged Like with JK, output would be unstable if transitions were not edge-triggered J K ck Q T (when T=1)

FAMU-FSU College of Engineering Pipelined Sequential Logic  What if your next-state logic becomes very deep and complicated? Its propagation delay will likely be high…  And this means your clock frequency will be low. This hurts the performance (throughput) of your design.  A widely-used approach to fix this problem: Divide your deep logic into some number d of sequential stages (where d is called the “pipeline depth”)…  with relatively shallow, fast logic between them You can then clock new inputs into the circuit at (nearly) d times higher frequency!  Side effect: Your design now maintains d states in parallel! Your application must be parallelizable for this to be helpful.  Note: Pipelining can improve throughput, but not the latency (time from input to output) to process individual data.

FAMU-FSU College of Engineering Non-pipelined vs. pipelined sequential designs For pipeline depth d=2:  Non-pipelined computes: x t+1 = z t = g(f(x t ))  Pipelined computes: y t+1 = f(x t ); x t+2 = z t+1 = g(y t+1 ) = g(f(x t ))  state on even cycles And simultaneously:  y t+2 = f(x t+1 ); x t+3 = z t+2 = g(y t+2 ) = g(f(x t+1 )) state on odd cycles clk g(f(x)) x z x f(x)f(x) y g(y)g(y) clk z Are both of these states representing something useful? Depends on your application! Slow clock Faster clock same function!