H-RORC HLT-Meeting CERN 02/06/05 Torsten Alt KIP Heidelberg.

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Presentation transcript:

H-RORC HLT-Meeting CERN 02/06/05 Torsten Alt KIP Heidelberg

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN H-RORC H-RORC : HLT-ReadOut-Receiver-Card Tasks: - Receiving of the raw detector data - Injecting the data in the main memory of the hosts of the HLT framework - Online processing of the data in hardware - Sending processed data out of the HLT Implementation: PCI card 64bit/66MHz with XILINX Virtex4 and external DDR-SDRAM

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN H-RORC details Xilinx Virtex4 LX40 FPGA PCI interface with 64bit up to 66MHz – XILINX LogiCORE 4 independent DDR-SDRAM modules with up to 1Gb ( each module is available in 128/256/512/1024 Mb) 2 x Half CMC to interface up to two SIU/DIU cards 2 independent configuration schemes “simple configuration” with Xilinx Platform Prom “smart configuration” with Flash and CPLD “Ready for Linux” – Ethernet interface, RS232 and Flash TagNet – Fast serial links to interconnect multiple RORCs

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN Virtex4 XC4VLX40 (640) 3.3V PCI 66/64 CMC HALF CPLD XC95144XL CFG-FLASH Max. 64MBit OSC JTAG Power 1V8 RS232 TAG-Net(LVDS) FastEthernet PHY LXT971A MII: 24 ROM-FLASH Max. 64MBit CMC HALF DDR-SDRAM 0 DDR-SDRAM 2 DDR-SDRAM 3 DDR-SDRAM 1 Power 1V2 Power 2V5 Power 3V3 Platform PROM 89 H-RORC blockdiagram

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN MT MX XC4LX40 PHY XCF XC95 Component layout

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN Virtex4 LX Logic Cells 288 Kb Distributed RAM ( x 16bit) 1728 Kb dual-port Block RAM (96 x 18KBit) 64 DSP slices : 18x18 two’s complement multiplier 48bit accumulator & adder/subtracter 8 Digital Clock Manager (DCM) 4 Phase-Matched Clock Dividers (PMCD) 640 User I/Os Flexible I/O technology : i.e. PCI, DDR, DDR2 partial/full reconfigurable while operating

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN “Simple configuration scheme” “Simple configuration” – the Virtex4 is configured via the Xilinx Platform PROM, a dedicated circuit for configuring Xilinx FPGAs PROM is Flash based and can be written by JTAG Virtex4 can be configured without a PC Used for standalone mode, i.e. Labs Redundant when operated in PC/HLT

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN “Smart configuration scheme” Virtex4 is configured out of the CFG Flash via a CPLD CFG Flash can have up to 4 independent configurations 1 Factory and 3 User configurations Factory configuration contains a small design that allows to write the user configurations over PCI and set an active flag Virtex4 is configured with the active user configuration CPLD has internal watchdog. This watchdog can be disabled by writing a special sequence from the Virtex4 to the CPLD to indicate a valid configuration If watchdog is not disabled within a certain time, it will assume a corrupt design in the Virtex4 and reload the Factory configuration

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN Writing configuration FAC USR CFG FLASH VIRTEX4 LX40 XC95144XL PCI

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN User configuration loaded FAC USR CFG FLASH VIRTEX4 LX40 XC95144XL PCI WATCHDOG

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN User configuration failed FAC USR CFG FLASH VIRTEX4 LX40 XC95144XL PCI WATCHDOG Loading factory default write sequence FAI LED

HLT-Meeting Torsten Alt KIP Heidelberg 02/06/05 CERN User configuration succeded FAC USR CFG FLASH VIRTEX4 LX40 XC95144XL PCI WATCHDOG write sequence