1 Chapter 4: Arithmetic for Computers (Part 2) CS 447 Jason Bakos.

Slides:



Advertisements
Similar presentations
Digital Circuits.
Advertisements

Cs 1110 Ch 4-1 Combinational Logic. ° Introduction Logic circuits for digital systems may be: °2°2 combinational sequential OR A combinational circuit.
Cosc 2150: Computer Organization Chapter 3: Boolean Algebra and Digital Logic.
Lecture 3 Karnaugh Map Chapter 2 Jack Ou, Ph.D.. Home Alarm Logic.
Addition (2). Outline Full Adder 3-Bit Adder 2’s Complement Subtraction.
1 Lecture 4: Arithmetic for Computers (Part 3) CS 447 Jason Bakos.
Computer Structure - The ALU Goal: Build an ALU  The Arithmetic Logic Unit or ALU is the device that performs arithmetic and logical operations in the.
Chapter 4: Arithmetic for Computers (Part 1)
Lecture 14 Today we will Learn how to implement mathematical logical functions using logic gate circuitry, using Sum-of-products formulation NAND-NAND.
30 September 2004Comp 120 Fall September 2004 Chapter 4 – Logic Gates Read in Chapter 4 pages , , section 4.8 through top of page.
Chap 3.3~3.5 Construction an Arithmetic Logic Unit (ALU) Jen-Chang Liu, Spring 2006.
CK Cheng Tuesday 10/2/02 CS 140 Lecture 2. Part I. Combinational Logic I) Specification –a. Language –b. Truth Table –c. Boolean Algebra –d. Incompletely.
Combinational Logic1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
Propositional Calculus Math Foundations of Computer Science.
Computer Science 210 Computer Organization The Arithmetic Logic Unit.
CS 105 Digital Logic Design
1 CHAPTER 4: PART I ARITHMETIC FOR COMPUTERS. 2 The MIPS ALU We’ll be working with the MIPS instruction set architecture –similar to other architectures.
Systems Architecture I1 Propositional Calculus Objective: To provide students with the concepts and techniques from propositional calculus so that they.
Combinational and Sequential Logic Circuits.
Binary Addition Section 4.5. Binary Addition Example.
Logic Gates Logic gates are electronic digital circuit perform logic functions. Commonly expected logic functions are already having the corresponding.
1 Arithmetic Logic Unit ALU. 2 The Bus Concept 3 CPU Building Blocks  Registers (IR, PC, ACC)  Control Unit (CU)  Arithmetic Logic Unit (ALU)
CS3350B Computer Architecture Winter 2015 Lecture 5.4: Combinational Logic Blocks Marc Moreno Maza [Adapted from lectures.
IT253: Computer Organization Lecture 7: Logic and Gates: Digital Design Tonga Institute of Higher Education.
Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO IO GNDI O Vcc Resister (limits conductivity) Truth Table.
Logic Design CS 270: Mathematical Foundations of Computer Science Jeremy Johnson.
1 Lecture 6 BOOLEAN ALGEBRA and GATES Building a 32 bit processor PH 3: B.1-B.5.
CDA 3101 Fall 2013 Introduction to Computer Organization The Arithmetic Logic Unit (ALU) and MIPS ALU Support 20 September 2013.
Lecture 18: Hardware for Arithmetic Today’s topic –Intro to Boolean functions (Continued) –Designing an ALU 1.
1 CS 151: Digital Design Chapter 4: Arithmetic Functions and Circuits 4-1,2: Iterative Combinational Circuits and Binary Adders.
Universal college of engineering & technology. .By Harsh Patel)
The Karnaugh Map.
MIPS ALU. Building from the adder to ALU ALU – Arithmetic Logic Unit, does the major calculations in the computer, including – Add – And – Or – Sub –
1  2004 Morgan Kaufmann Publishers Performance is specific to a particular program/s –Total execution time is a consistent summary of performance For.
Appendix C Basics of Digital Logic Part I. Florida A & M University - Department of Computer and Information Sciences Modern Computer Digital electronics.
1  2004 Morgan Kaufmann Publishers Lets Build a Processor Almost ready to move into chapter 5 and start building a processor First, let’s review Boolean.
CEC 220 Digital Circuit Design
Chapter 3 Digital Logic Structures
Mehmet Can Vuran, Instructor University of Nebraska-Lincoln Acknowledgement: Schematics adapted from those provided by the authors Hennessey and Patterson.
Gates AND, OR, NOT NAND, NOR Combinational logic No memory A set of inputs uniquely and unambiguously specifies.
1 Lecture 11: Hardware for Arithmetic Today’s topics:  Logic for common operations  Designing an ALU  Carry-lookahead adder.
1 Arithmetic Where we've been: –Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: –Implementing the Architecture.
MIPS ALU. Exercise – Design a selector? I need a circuit that takes two input bits, a and b, and a selector bit s. The function is that if s=0, f=a. if.
Simple ALU  Half adder  Full adder  Constructing 4 bits adder  ALU does several operations  General ALU structure  Timing diagram of adder  Overflow.
CS151 Introduction to Digital Design Chapter 4: Arithmetic Functions and HDLs 4-1: Iterative Combinational Circuits 4-2: Binary Adders 1Created by: Ms.Amany.
Full Adders Vector Notation Multiplexers and Decoders Ellen Spertus MCS 111 September 6, 2001.
Chapter 12. Chapter Summary Boolean Functions Representing Boolean Functions Logic Gates Minimization of Circuits (not currently included in overheads)
Combinational Circuits
ECE 3130 Digital Electronics and Design
CS 270: Mathematical Foundations of Computer Science
ECE 3130 Digital Electronics and Design
Lecture 11: Hardware for Arithmetic
Computer Science 210 Computer Organization
Combinational Circuits
MIPS ALU.
5. Combinational circuits
MIPS ALU.
EEL 3705 / 3705L Digital Logic Design
Digital Logic.
Lecture 11: Hardware for Arithmetic
COSC 2021: Computer Organization Instructor: Dr. Amir Asif
Adders and Subtractors
Digital Logic.
COMS 361 Computer Organization
Combinational Circuits
XOR Function Logic Symbol  Description  Truth Table 
Half & Full Subtractor Half Subtractor Full Subtractor.
Half & Full Subtractor Half Subtractor Full Subtractor.
MIPS ALU.
MIPS ALU.
Presentation transcript:

1 Chapter 4: Arithmetic for Computers (Part 2) CS 447 Jason Bakos

2 Logic/Arithmetic From the truth table for the mux, we can use sum-of-products to derive the logic equation –With sum-of-products, for each ‘1’ row for each output, we AND together all the inputs (inverting the input 0’s), then OR all the row products To make it simpler, let’s add “don’t cares” to the table…

3 Logic/Arithmetic This gives us the following equation –(A and (not D)) or (B and D) –We don’t need the inputs for the “don’t cares” in our partial products –This is one way to simplify our logic equation Other ways include propositional calculus, Karnaugh Maps, and the Quine-McCluskey algorithm ABDC (out) 0X00 (a) X010 (b) 1X01 (a) X111 (b)

4 Logic/Arithmetic Here is a (crude) digital logic design for the 2-to-1 mux Note that multiple muxes can be assembled in stages to implement multiple-input muxes

5 Logic/Arithmetic For the adder, let’s minimize the logic using a Karnaugh Map… For CarryOut, we need 2 3 entries… We can minimize this to –CarryOut=AB+CarryInB+CarryInC AB CarryIn

6 Logic/Arithmetic There’s no way to minimize this equation, so we need the full sum of products: –Sum=(not A)(not B)CarryIn + ABCarryIn + (not A)BCarryIn + A(not B)CarryIn AB CarryIn

7 Logic/Arithmetic In order to implement subtraction, we can invert the B input to the adder and set CarryIn to be 1 –This can be implemented with a mux: select B or not B (call this input Binvert) Now we can build a 1-bit ALU using an AND, OR, addition, and subtraction operation –We can perform the AND, OR, and ADD in parallel and switch the results with a 4-input mux (Operation will be our D-input) –To make the adder a subtractor, we’ll need to have to set Binvert and CarryIn to 1