Feb 2002 HTR Status CMS HCal meeting at FIT Feb. 7-9, 2002 Tullio Grassi University of Maryland

Feb 2002 HCAL FE/DAQ Overview Shield Wall BIT3BIT3 DAQ RUI HPD FE MODULE  18 HTRs per Readout Crate FRONT-END RBX Readout Box (On detector) READ-OUT Crate (in UXA) Trigger Primitives Fibers at 1.6 Gb/s 3 QIE-channels per fiber (data format defined) QIE CCA GOL DCCDCC TTC GOL CCA HTRHTR HTRHTR HTRHTR CAL REGIONAL TRIGGER MHz MHz CCA Trigger DAQ

Feb 2002 Readout - 9U VME crate Cal. Regional Trigger 20 m Copper Links 1 Gb/s Trig DAQ Gbit 1.6 Gb/s Front End Electronics TTC fiber HTRHTR HTRHTR HTRHTR HTRHTR DCCDCC FanOut FanOut BIT3BIT S L B 6- S L B 6- S L B 6- S L B DAQ Slink64 BIT3-like 6U board Commercial module Slow monitoring FanOut board FanOut of TTC stream FanOut of RX_CK & RX_BC0 HTR ( HCAL Trigger and Readout ) FE-Fiber input TPs output to HEX-SLB DAQ/TP Data output to DCC Spy VME output DCC (Data Concentrator Card) Input from HTRs Output to DAQ & TrigDAQ Spy VME output

Feb 2002 H CAL T RIGGER and R EADOUT Card Front panel: –FE-data Inputs: 16 digital serial fibers, 3 QIE channels per fiber –Timing Inputs: clock, BC0, etc (LVDS; RJ-45 connector) –DAQ-data Output to DCC: 2 Channel Links FPGA logic: –L1/Trigger Path: Trigger primitive preparation and transmission –L2/DAQ Path: Waiting for L1 Decision, filtering or BCID (?), transm. to DCC –VME Interface, slow control Transition board (HEX-SLB): –Receives Trigger Primitives via standard P2/P3 (280 Mb/s // LVDS) –Holds 6 SLB daughterboards –Transmission with Vitesse/shielded twisted pair

Feb 2002 HTR - baseline Transition Board (HEX-SLB) OPTICAL RX P1 OPTICAL RX P2 LVDS TX P3 SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) SLB -PMC (ECAL design) Trigger output 48 Trigger Towers 9U Board FPGA FPGA 90% defined specs and interface DES Timing Interface defined

Feb 2002 Changes Demonstrator  Prototype FE input : 800 Mb/s  1.6 Gb/s # of QIE-channels:16x2  12x3  16x3 Timing input : TTC board  TTC chip Core logic: Altera  Xilinx Trigger output:  on the new Transition board Form factor: 6U  9U Things that remain unchanged DAQ output : Channel Link

Feb 2002 HTR Pre-Prototype Received: Nov 2001 Included:Optical input, Xilinx FBGA logic, DAQ output, VME. Not included:TTC input, Trigger output. IMPLEMENTATION DETAILS: Hi-Speed differential lines: matched in single-end Z c and length (20 mils); max length ~ 5 inches; no vias (TI approach). ‘Thermal land’ underneath the TI chips. Separate VDD and VDDA planes + filters. Parallel data lines: 80 Mb/s, minimized length, no vias, serial dumping resistor. Clever pin-assignement on Xilinx

Feb 2002 Zoom on Pre-Prototype lay-out TI Xilinx Dual LC receiver DAQ out Dual LC receiver

Feb 2002 Results from testing Xilinx FBGA and VME circuitry passed basic testings. Optical input not working. These changes were unsuccessfull: Shortening the high-speed path (Connecting the optical receiver directly to the TI deserializer). Using different optical receivers. Providing a better reference clock. Playing with analog levels and decoupling capacitors. Reduce noise on VDD (all FPGAs unprogrammed).

Feb 2002 Possible reasons for failure Wrong footprint for TI part (bigger than the chip)  company refused to assemble TI part  in-home assembly: no temperature control Geometry of V DDA and V DD planes  digital noise Reference clock without PLL driver  jitter

Feb 2002 Link-only board All mentioned reasons were eliminated. The board includes also Tracker-like and electrical inputs.

Feb 2002 Link-only board All mentioned reasons were eliminated. The board includes also Tracker-like and electrical inputs. Testing Results: works (only with controlled assembly) New issues (compared to G-link): Jitter Max offset on frequency Need more investigation (with FNAL)

Feb 2002 HTR prototype Lay-out 90% complete according to the baseline scheme and test results of the Link-only board. TTCrx parts needed Submission in March ?

Feb 2002 Data Paths DAQ-path: we have a basic firmware: 24 channels/FPGA 10 samples/event (raw QIE data) Max trigger rate (peak) ~ 150 kHz Adjustable L1-latency pipeline No Zero-Suppression No BCID Next steps: Improve sustainable trigger rate Zero-Suppression on raw data ? BCID Trigger Path: contribution from Princeton ?

Feb 2002 Near future Investigation timing issues  applied to prototype design Defininition of the DAQ-path for the Test Beam Definition of the timing requirements for the Test Beam Integration with the Fanout board and FE board Definition of backplane (for Transition Board power) HO requirement on our trigger path/link

Feb Demonstrator Requirements Resources Links 6U board Prototype New I/Os Simple Algorithm Pre-Prod Freeze hardware Algorithm for 90º Production Test bench, Special algorithms Slice Test I Project Timeline FNAL source calib. Cern Test Beam 2004 Slice Test II Pre-production very short. Test bench before production ? Slice Test I with pre-production ?