FPGA Ethernetlink to DAQ level translation SMA/ LEMO RJ45 TLU Virtex 6 6 HDMI fanout HDMI OUT e.g. DCC-fanout HDMI IN Xilinx ML605-Board global clock trigger.

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Presentation transcript:

FPGA Ethernetlink to DAQ level translation SMA/ LEMO RJ45 TLU Virtex 6 6 HDMI fanout HDMI OUT e.g. DCC-fanout HDMI IN Xilinx ML605-Board global clock trigger diff local clock

FPGA MUX clocks clk fanout trigger fanout trigger etc. algorithms/ combinatorial local clock to HDMI 1 from HDMI bussy

FPGA MUX clocks clk fanout trigger fanout trigger etc. algorithms/ combinatorial local clock to HDMI 1 from HDMI bussy

level translation SMA LEMO 8 HDMI fanout HDMI IN global clock trigger local clock CPLD combinatorial MUX