הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל המעבדה למערכות ספרתיות מהירות Characterization Presentation Enhanced Ethernet Card Enhanced Ethernet Card Project num Students: Alex Shpiner Eyal Azran Supervisor: Boaz Mizrahi

Present Architecture FPGA PLXPLX MACMAC PHYPHY PCIPCI ETHERNETETHERNET Current Main Features: Transmitting and Receiving Ethernet frames Transmitting and Receiving Ethernet frames MAC and PHY configuration control MAC and PHY configuration control

PCIBRIDGEPCIBRIDGE MACMAC PHY CIFCIF GNR MCF TRN RCV ARB Present FPGA Block Diagram Shared bus

Project’s goals:   Automatic ping reply

Project’s goals:   Automatic ping reply   Real time Packet analyzer & data collector

Project’s goals:   Automatic ping reply   Real time Packet analyzer & data collector   Real time Network Testing Unit:

Project’s goals:   Automatic ping reply   Real time Packet analyzer & data collector   Real time Network Testing Unit:   Predefined transmit rate

Project’s goals:   Automatic ping reply   Real time Packet analyzer & data collector   Real time Network Testing Unit:   Predefined transmit rate   Accurate measurement of response time

Project’s goals:   Automatic ping reply   Real time Packet analyzer & data collector   Real time Network Testing Unit:   Predefined transmit rate   Accurate measurement of response time   Testing parameters are predefined by user

MACMAC CIFCIF TRN RCV ARB FPGA Architecture Shared bus TRP RCP * Configuration units (GNR, MCF) are not shown on this diagram

RCP – Receive Processing Unit Regular Packets Received Data Collector Packet Analyzer CIFCIF RCVRCV TRP RCP

TRP – Transmit Processing Unit Echo Request Parameters Regular Packets to be transmitted Echo Request Generator Echo Reply Creator TRN Arbiter CIFCIF TRNTRN RCP TRP

Project Achievements Learning network protocols (Ethernet, IP, Echo). Experience in advanced VHDL. Appropriate unit design and simulation. Organized work and documentation.

Approximated Time Table Time line Learning the Network Protocols Architecture Design and Algorithms Development Final Presentation and Project Book Submitting Writing the code and simulation Synthesis & Debug March 2004 April 2004 May to June 2004 Jule 2004 August 2004

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