1 Sequential Logic The Forbidden Zone Ellen Spertus MCS 111 September 10 and 12, 2002

2 What does a computer do? Calculates mathematical functions Allows different operations to be specified

3 Combinational logic Everything we’ve done so far Outputs depend only on the inputs No cycles (loops)

4 Sequential logic What we’ll look at this week Outputs depend on –inputs –previous values (“state”) Cycles (loops) in circuits Purpose?

5 Useful memory unit Remember old value Set to high Reset to low

6 RS-latch symbol and truth table Q = R + ~Q ~Q = S + Q

7 RS-latch implementation Q = R + ~Q ~Q = S + Q

8 RS-latch timing diagram

9 RS-latch dangerous transition 1  01  0 1  01  0 0 0  0 0 

10 Low-level summary Meaning of RS? –R –S Behavior –R=0, S=0  –R=0, S=1  –R=1, S=0  –R=1, S=1 

11 High-level summary: RS latch Capabilities: Limitations: What improvements would we like?

12 Preventing forbidden transition How can we prevent R and S from simultaneously changing from 1 to 0?

13 D-latch

14 D-latch behavior

15

16 4-bit D-latch

17 Counter: first attempt

Behind the Curtain18 Behind the curtain

Behind the Curtain19 Representation of 0s and 1s Logical zero (false):0 –.8 Volts Logical one (high):2 – 5 Volts What is:.4 Volts 3.5 Volts 1.2 Volts

Behind the Curtain20 The Forbidden Zone A range of voltages that represent neither zero nor one; specifically:

Behind the Curtain21 Inverter (not gate) behavior If input voltage is low, output is: If input voltage is high, output is: In input voltage is in between, output is: 0 5

Behind the Curtain22 How to deal with forbidden zone ? Never allow any point in the circuit to have a voltage in the forbidden zone.

Behind the Curtain23 A closer look at a “square” wave time voltage

Behind the Curtain24 We can’t avoid the forbidden zone You can’t get from here to there without going in between.

Behind the Curtain25 How to deal with forbidden zone ? Never allow any point in the circuit to have a voltage in the forbidden zone. Never allow a value in the forbidden zone to be an input to a gate.

Behind the Curtain26 Propagation delays Every gate has a propagation delay, the time it takes to make the complete transition. During this period, the result may be in the forbidden zone. After the propagation delay, the result will not be in the forbidden zone.

Behind the Curtain27 Combined propagation delays If each gate has a propagation delay of 5 ns, what is the total propagation delay? Meaning:

Behind the Curtain28 How to deal with forbidden zone? Never allow any point in the circuit to have a voltage in the forbidden zone. Never allow a value in the forbidden zone to be an input to a gate. Don’t look at an output until after the propagation delay.

29 Counter: first attempt

30 The problem If we have cycles in our circuit, values in the forbidden region will propagate through the circuit, contaminating all data.

31 How to deal with forbidden zone ? Don’t look at an output until after the propagation delay -If no loops, just wait out propagation delay -If loops, insert a barrier to prevent forbidden values from contaminating the rest of the circuit

32 D flip-flop

33 D flip-flop behavior Only accept new data when Otherwise, keep the same data

34 Counter: correct

35 Counter: correct (close-up)

36 Timing diagram

37 LS377: octal D-type flip-flop OE = output enable (active low) Inputs D7-D0 Outputs Q7-Q0 Clock input

38 Wiring diagrams Shows logical shape Has chip number Includes pin numbers in logical order (outside chip) Includes signal names (inside chip) Bubble indicates active-low input “nc” stands for:

39 Looking ahead Assignments –Lab 1 due tomorrow (September 13) –Homework 3 due Tuesday (September 19) –Lab 2 due next Friday (September 20) Topics –You now know the basics –Start studying assembly language from Hennessy and Patterson